3 * @author Lunaixsky (zelong56@gmail.com)
4 * @brief A software implementation of Serial ATA AHCI 1.3.1 Specification
8 * @copyright Copyright (c) 2022
13 #include <klibc/string.h>
14 #include <lunaix/mm/kalloc.h>
15 #include <lunaix/mm/mmio.h>
16 #include <lunaix/mm/pmm.h>
17 #include <lunaix/spike.h>
18 #include <lunaix/syslog.h>
20 #define HBA_FIS_SIZE 256
21 #define HBA_CLB_SIZE 1024
25 static struct ahci_hba hba;
30 struct pci_device* ahci_dev = pci_get_device_by_class(AHCI_HBA_CLASS);
31 assert_msg(ahci_dev, "AHCI: Not found.");
34 size = pci_bar_sizing(ahci_dev, &bar6, 6);
35 assert_msg(bar6 && PCI_BAR_MMIO(bar6), "AHCI: BAR#6 is not MMIO.");
37 pci_reg_t cmd = pci_read_cspace(ahci_dev->cspace_base, PCI_REG_STATUS_CMD);
39 // 禁用传统中断(因为我们使用MSI),启用MMIO访问,允许PCI设备间访问
40 cmd |= (PCI_RCMD_MM_ACCESS | PCI_RCMD_DISABLE_INTR | PCI_RCMD_BUS_MASTER);
42 pci_write_cspace(ahci_dev->cspace_base, PCI_REG_STATUS_CMD, cmd);
44 hba.base = (hba_reg_t*)ioremap(PCI_BAR_ADDR_MM(bar6), size);
47 hba.base[HBA_RGHC] |= HBA_RGHC_RESET;
48 wait_until(!(hba.base[HBA_RGHC] & HBA_RGHC_RESET));
51 hba.base[HBA_RGHC] |= (HBA_RGHC_ACHI_ENABLE | HBA_RGHC_INTR_ENABLE);
53 // As per section 3.1.1, this is 0 based value.
54 hba_reg_t cap = hba.base[HBA_RCAP];
55 hba.ports_num = (cap & 0x1f) + 1; // CAP.PI
56 hba.cmd_slots = (cap >> 8) & 0x1f; // CAP.NCS
57 hba.version = hba.base[HBA_RVER];
59 /* ------ HBA端口配置 ------ */
60 hba_reg_t pmap = hba.base[HBA_RPI];
61 uintptr_t clb_pg_addr, fis_pg_addr, clb_pa, fis_pa;
62 for (size_t i = 0, fisp = 0, clbp = 0; i < 32;
63 i++, pmap >>= 1, fisp = (fisp + 1) % 16, clbp = (clbp + 1) % 4) {
68 struct ahci_port* port =
69 (struct ahci_port*)lxmalloc(sizeof(struct ahci_port));
70 hba_reg_t* port_regs =
71 (hba_reg_t*)(&hba.base[HBA_RPBASE + i * HBA_RPSIZE]);
75 clb_pa = pmm_alloc_page(KERNEL_PID, PP_FGLOCKED);
76 clb_pg_addr = ioremap(clb_pa, 0x1000);
77 memset(clb_pg_addr, 0, 0x1000);
81 fis_pa = pmm_alloc_page(KERNEL_PID, PP_FGLOCKED);
82 fis_pg_addr = ioremap(fis_pa, 0x1000);
83 memset(fis_pg_addr, 0, 0x1000);
87 port_regs[HBA_RPxCLB] = clb_pa + clbp * HBA_CLB_SIZE;
88 port_regs[HBA_RPxFB] = fis_pa + fisp * HBA_FIS_SIZE;
91 (struct ahci_port){ .regs = port_regs,
92 .ssts = port_regs[HBA_RPxSSTS],
93 .cmdlstv = clb_pg_addr + clbp * HBA_CLB_SIZE,
94 .fisv = fis_pg_addr + fisp * HBA_FIS_SIZE };
97 port_regs[HBA_RPxCI] = 0;
98 port_regs[HBA_RPxIE] |= (HBA_PxINTR_DMA | HBA_PxINTR_D2HR);
99 port_regs[HBA_RPxCMD] |= (HBA_PxCMD_FRE | HBA_PxCMD_ST);
105 char sata_ifs[][20] = { "Not detected",
108 "SATA III (6.0Gbps)" };
113 kprintf(KINFO "Version: %x; Ports: %d\n", hba.version, hba.ports_num);
114 for (size_t i = 0; i < 32; i++) {
115 struct ahci_port* port = hba.ports[i];
118 kprintf("\t Port %d: %s\n", i, &sata_ifs[HBA_RPxSSTS_IF(port->ssts)]);