lunaix-os/hal/gfxa/vga/vga_pci.c

   1 #include <lunaix/device.h>
   2 #include <lunaix/mm/mmio.h>
   3 #include <lunaix/mm/valloc.h>
   4 #include <lunaix/spike.h>
   5 #include <lunaix/status.h>
   6
   7 #include <hal/gfxm.h>
   8 #include <hal/pci.h>
   9 #include <sys/pci_hba.h>
  10
  11 #include <klibc/string.h>
  12
  13 #include "vga.h"
  14
  15 extern struct vga_regops vga_default_mmio_ops;
  16
  17 #define FB256K 256 << 10
  18
  19 static u32_t palette[] = {
  20     0x000000, 0x800000, 0x008000, 0x808000, 0x000080, 0x800080, 0x008080,
  21     0xc0c0c0, 0x808080, 0xff0000, 0x00ff00, 0xffff00, 0x0000ff, 0xff00ff,
  22     0x00ffff, 0xffffff, 0x000000, 0x00005f, 0x000087, 0x0000af, 0x0000d7,
  23     0x0000ff, 0x005f00, 0x005f5f, 0x005f87, 0x005faf, 0x005fd7, 0x005fff,
  24     0x008700, 0x00875f, 0x008787, 0x0087af, 0x0087d7, 0x0087ff, 0x00af00,
  25     0x00af5f, 0x00af87, 0x00afaf, 0x00afd7, 0x00afff, 0x00d700, 0x00d75f,
  26     0x00d787, 0x00d7af, 0x00d7d7, 0x00d7ff, 0x00ff00, 0x00ff5f, 0x00ff87,
  27     0x00ffaf, 0x00ffd7, 0x00ffff, 0x5f0000, 0x5f005f, 0x5f0087, 0x5f00af,
  28     0x5f00d7, 0x5f00ff, 0x5f5f00, 0x5f5f5f, 0x5f5f87, 0x5f5faf, 0x5f5fd7,
  29     0x5f5fff, 0x5f8700, 0x5f875f, 0x5f8787, 0x5f87af, 0x5f87d7, 0x5f87ff,
  30     0x5faf00, 0x5faf5f, 0x5faf87, 0x5fafaf, 0x5fafd7, 0x5fafff, 0x5fd700,
  31     0x5fd75f, 0x5fd787, 0x5fd7af, 0x5fd7d7, 0x5fd7ff, 0x5fff00, 0x5fff5f,
  32     0x5fff87, 0x5fffaf, 0x5fffd7, 0x5fffff, 0x870000, 0x87005f, 0x870087,
  33     0x8700af, 0x8700d7, 0x8700ff, 0x875f00, 0x875f5f, 0x875f87, 0x875faf,
  34     0x875fd7, 0x875fff, 0x878700, 0x87875f, 0x878787, 0x8787af, 0x8787d7,
  35     0x8787ff, 0x87af00, 0x87af5f, 0x87af87, 0x87afaf, 0x87afd7, 0x87afff,
  36     0x87d700, 0x87d75f, 0x87d787, 0x87d7af, 0x87d7d7, 0x87d7ff, 0x87ff00,
  37     0x87ff5f, 0x87ff87, 0x87ffaf, 0x87ffd7, 0x87ffff, 0xaf0000, 0xaf005f,
  38     0xaf0087, 0xaf00af, 0xaf00d7, 0xaf00ff, 0xaf5f00, 0xaf5f5f, 0xaf5f87,
  39     0xaf5faf, 0xaf5fd7, 0xaf5fff, 0xaf8700, 0xaf875f, 0xaf8787, 0xaf87af,
  40     0xaf87d7, 0xaf87ff, 0xafaf00, 0xafaf5f, 0xafaf87, 0xafafaf, 0xafafd7,
  41     0xafafff, 0xafd700, 0xafd75f, 0xafd787, 0xafd7af, 0xafd7d7, 0xafd7ff,
  42     0xafff00, 0xafff5f, 0xafff87, 0xafffaf, 0xafffd7, 0xafffff, 0xd70000,
  43     0xd7005f, 0xd70087, 0xd700af, 0xd700d7, 0xd700ff, 0xd75f00, 0xd75f5f,
  44     0xd75f87, 0xd75faf, 0xd75fd7, 0xd75fff, 0xd78700, 0xd7875f, 0xd78787,
  45     0xd787af, 0xd787d7, 0xd787ff, 0xd7af00, 0xd7af5f, 0xd7af87, 0xd7afaf,
  46     0xd7afd7, 0xd7afff, 0xd7d700, 0xd7d75f, 0xd7d787, 0xd7d7af, 0xd7d7d7,
  47     0xd7d7ff, 0xd7ff00, 0xd7ff5f, 0xd7ff87, 0xd7ffaf, 0xd7ffd7, 0xd7ffff,
  48     0xff0000, 0xff005f, 0xff0087, 0xff00af, 0xff00d7, 0xff00ff, 0xff5f00,
  49     0xff5f5f, 0xff5f87, 0xff5faf, 0xff5fd7, 0xff5fff, 0xff8700, 0xff875f,
  50     0xff8787, 0xff87af, 0xff87d7, 0xff87ff, 0xffaf00, 0xffaf5f, 0xffaf87,
  51     0xffafaf, 0xffafd7, 0xffafff, 0xffd700, 0xffd75f, 0xffd787, 0xffd7af,
  52     0xffd7d7, 0xffd7ff, 0xffff00, 0xffff5f, 0xffff87, 0xffffaf, 0xffffd7,
  53     0xffffff, 0x080808, 0x121212, 0x1c1c1c, 0x262626, 0x303030, 0x3a3a3a,
  54     0x444444, 0x4e4e4e, 0x585858, 0x626262, 0x6c6c6c, 0x767676, 0x808080,
  55     0x8a8a8a, 0x949494, 0x9e9e9e, 0xa8a8a8, 0xb2b2b2, 0xbcbcbc, 0xc6c6c6,
  56     0xd0d0d0, 0xdadada, 0xe4e4e4, 0xeeeeee
  57 };
  58
  59 #define VGA_REG_OFF 0x0400
  60
  61 static int
  62 vga_pci_init(struct device_def* devdef, struct device* pcidev_base)
  63 {
  64     struct pci_device* pcidev = PCI_DEVICE(pcidev_base);
  65
  66     struct pci_base_addr* fb = &pcidev->bar[0];
  67     struct pci_base_addr* mmio = &pcidev->bar[2];
  68
  69     if (PCI_BAR_ADDR_IO(mmio->type)) {
  70         return EINVAL;
  71     }
  72
  73     pci_reg_t cmd = pci_read_cspace(pcidev->cspace_base, PCI_REG_STATUS_CMD);
  74
  75     cmd |= (PCI_RCMD_MM_ACCESS | PCI_RCMD_DISABLE_INTR | PCI_RCMD_BUS_MASTER);
  76
  77     pci_write_cspace(pcidev->cspace_base, PCI_REG_STATUS_CMD, cmd);
  78
  79     ptr_t fb_mapped = (ptr_t)ioremap(fb->start, FB256K);
  80     ptr_t mmio_mapped = (ptr_t)ioremap(mmio->start, mmio->size);
  81
  82     struct vga* vga_state =
  83       vga_new_state(mmio_mapped + VGA_REG_OFF, fb_mapped, FB256K);
  84     vga_state->reg_ops = vga_default_mmio_ops;
  85
  86     struct gfxa* vga_gfxa = gfxm_alloc_adapter(vga_state);
  87     extern struct gfxa_ops vga_gfxa_ops;
  88     vga_gfxa->ops = vga_gfxa_ops;
  89
  90     // Preload a VESA-compilant configuration
  91     vga_gfxa->disp_info = (struct disp_profile){
  92         .mon = { .w_px = 640, .h_px = 480, .freq = 60, .depth = 16 }
  93     };
  94
  95     gfxm_register(vga_gfxa);
  96
  97     return 0;
  98 }
  99
 100 #define VGA_PCI_CLASS 0x30000
 101
 102 static struct pci_device_def vga_pci_devdef = {
 103     .dev_class = VGA_PCI_CLASS,
 104     .dev_ident = PCI_DEVIDENT(0x1234, 0x1111),
 105     .ident_mask = PCI_MATCH_EXACT,
 106     .devdef = { .class = DEVCLASS(DEVIF_PCI, DEVFN_DISP, DEV_VGA),
 107                 .name = "Generic VGA",
 108                 .init_for = vga_pci_init }
 109 };
 110 EXPORT_PCI_DEVICE(vga_pci, &vga_pci_devdef);