3 #include <lunaix/mm/kalloc.h>
4 #include <lunaix/syslog.h>
8 static struct llist_header pci_devices;
11 pci_probe_msi_info(struct pci_device* device);
14 pci_probe_device(int bus, int dev, int funct)
16 uint32_t base = PCI_ADDRESS(bus, dev, funct);
17 pci_reg_t reg1 = pci_read_cspace(base, 0);
19 // Vendor=0xffff则表示设备不存在
20 if (PCI_DEV_VENDOR(reg1) == PCI_VENDOR_INVLD) {
24 pci_reg_t hdr_type = pci_read_cspace(base, 0xc);
25 hdr_type = (hdr_type >> 16) & 0xff;
27 if ((hdr_type & 0x80)) {
28 hdr_type = hdr_type & ~0x80;
29 // 探测多用途设备(multi-function device)
30 for (int i = 1; i < 7; i++) {
31 pci_probe_device(bus, dev, i);
35 if (hdr_type != PCI_TDEV) {
36 // XXX: 目前忽略所有桥接设备,比如PCI-PCI桥接器,或者是CardBus桥接器
40 pci_reg_t intr = pci_read_cspace(base, 0x3c);
41 pci_reg_t class = pci_read_cspace(base, 0x8);
43 struct pci_device* device = lxmalloc(sizeof(struct pci_device));
44 *device = (struct pci_device){ .cspace_base = base,
49 pci_probe_msi_info(device);
51 llist_append(&pci_devices, &device->dev_chain);
58 // XXX: 尽管最多会有256条PCI总线,但就目前而言,只考虑bus #0就足够了
59 for (int bus = 0; bus < 1; bus++) {
60 for (int dev = 0; dev < 32; dev++) {
61 pci_probe_device(bus, dev, 0);
67 pci_probe_msi_info(struct pci_device* device)
70 pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16;
72 if (!(status & 0x10)) {
77 pci_reg_t cap_ptr = pci_read_cspace(device->cspace_base, 0x34) & 0xff;
81 cap_hdr = pci_read_cspace(device->cspace_base, cap_ptr);
82 if ((cap_hdr & 0xff) == 0x5) {
84 device->msi_loc = cap_ptr;
87 cap_ptr = (cap_hdr >> 8) & 0xff;
91 #define PCI_PRINT_BAR_LISTING
96 struct pci_device *pos, *n;
97 llist_for_each(pos, n, &pci_devices, dev_chain)
99 kprintf(KINFO "(B%xh:D%xh:F%xh) Dev %x:%x, Class 0x%x\n",
100 PCI_BUS_NUM(pos->cspace_base),
101 PCI_SLOT_NUM(pos->cspace_base),
102 PCI_FUNCT_NUM(pos->cspace_base),
103 PCI_DEV_VENDOR(pos->device_info),
104 PCI_DEV_DEVID(pos->device_info),
105 PCI_DEV_CLASS(pos->class_info));
107 kprintf(KINFO "\t IRQ: %d, INT#x: %d\n",
108 PCI_INTR_IRQ(pos->intr_info),
109 PCI_INTR_PIN(pos->intr_info));
110 #ifdef PCI_PRINT_BAR_LISTING
112 for (size_t i = 1; i <= 6; i++) {
113 size_t size = pci_bar_sizing(pos, &bar, i);
116 if (PCI_BAR_MMIO(bar)) {
117 kprintf(KINFO "\t BAR#%d (MMIO) %p [%d]\n",
119 PCI_BAR_ADDR_MM(bar),
122 kprintf(KINFO "\t BAR#%d (I/O) %p [%d]\n",
124 PCI_BAR_ADDR_IO(bar),
130 kprintf(KINFO "\t MSI supported (@%xh)\n", pos->msi_loc);
136 pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
138 pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num));
144 pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), 0xffffffff);
146 pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)) & ~0x1;
147 if (PCI_BAR_MMIO(bar)) {
148 sized = PCI_BAR_ADDR_MM(sized);
155 pci_setup_msi(struct pci_device* device, int vector)
157 // Dest: APIC#0, Physical Destination, No redirection
158 uint32_t msi_addr = (__APIC_BASE_PADDR | 0x8);
160 // Edge trigger, Fixed delivery
161 uint32_t msi_data = vector;
164 device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
166 device->cspace_base, PCI_MSI_DATA(device->msi_loc), msi_data & 0xffff);
168 pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
170 // manipulate the MSI_CTRL to allow device using MSI to request service.
171 reg1 = ((((reg1 >> 16) & ~0x70) | 0x1) << 16) | (reg1 & 0xffff);
172 pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
176 pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId)
178 uint32_t dev_info = vendorId | (deviceId << 16);
179 struct pci_device *pos, *n;
180 llist_for_each(pos, n, &pci_devices, dev_chain)
182 if (pos->device_info == dev_info) {
191 pci_get_device_by_class(uint32_t class)
193 struct pci_device *pos, *n;
194 llist_for_each(pos, n, &pci_devices, dev_chain)
196 if (PCI_DEV_CLASS(pos->class_info) == class) {
207 llist_init_head(&pci_devices);