5 #include <lunaix/ds/llist.h>
7 #define PCI_CONFIG_ADDR 0xcf8
8 #define PCI_CONFIG_DATA 0xcfc
11 #define PCI_TPCIBRIDGE 0x1
12 #define PCI_TCARDBRIDGE 0x2
14 #define PCI_VENDOR_INVLD 0xffff
16 #define PCI_REG_VENDOR_DEV 0
17 #define PCI_REG_STATUS_CMD 0x4
18 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
20 #define PCI_DEV_VENDOR(x) ((x)&0xffff)
21 #define PCI_DEV_DEVID(x) ((x) >> 16)
22 #define PCI_INTR_IRQ(x) ((x)&0xff)
23 #define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
24 #define PCI_DEV_CLASS(x) ((x) >> 8)
25 #define PCI_DEV_REV(x) (((x)&0xff))
26 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
27 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
28 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
30 #define PCI_BAR_MMIO(x) (!((x)&0x1))
31 #define PCI_BAR_CACHEABLE(x) ((x)&0x8)
32 #define PCI_BAR_TYPE(x) ((x)&0x6)
33 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
34 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
36 #define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
37 #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
38 #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
40 #define MSI_CAP_64BIT 0x80
41 #define MSI_CAP_MASK 0x100
42 #define MSI_CAP_ENABLE 0x1
44 #define PCI_RCMD_DISABLE_INTR (1 << 10)
45 #define PCI_RCMD_FAST_B2B (1 << 9)
46 #define PCI_RCMD_BUS_MASTER (1 << 2)
47 #define PCI_RCMD_MM_ACCESS (1 << 1)
48 #define PCI_RCMD_IO_ACCESS 1
50 #define PCI_ADDRESS(bus, dev, funct) \
51 (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) | \
54 typedef unsigned int pci_reg_t;
56 // PCI device header format
57 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
59 #define BAR_TYPE_MMIO 0x1
60 #define BAR_TYPE_CACHABLE 0x2
71 struct llist_header dev_chain;
77 struct pci_base_addr bar[6];
80 // PCI Configuration Space (C-Space) r/w:
81 // Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
83 static inline pci_reg_t
84 pci_read_cspace(uint32_t base, int offset)
86 io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
87 return io_inl(PCI_CONFIG_DATA);
91 pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
93 io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
94 io_outl(PCI_CONFIG_DATA, data);
98 * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意,该
99 * 初始化不包括针对每个设备的初始化,因为那是设备驱动的事情。
106 * @brief 根据类型代码(Class Code)去在拓扑中寻找一个设备
107 * 类型代码请参阅: PCI LB Spec. Appendix D.
109 * @return struct pci_device*
111 struct pci_device* pci_get_device_by_class(uint32_t class);
114 * @brief 根据设备商ID和设备ID,在拓扑中寻找一个设备
118 * @return struct pci_device*
121 pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
124 * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的,
125 * 设备所使用的MMIO或I/O地址空间的,大小。
126 * 参阅:PCI LB Spec. (Rev 3) Section 6.2.5.1, Implementation Note.
128 * @param dev The PCI device
129 * @param bar_out Value in BAR
130 * @param bar_num The index of BAR (starting from 1)
134 pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
137 * @brief 配置并启用设备MSI支持。
138 * 参阅:PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
139 * 以及:Intel Manual, Vol 3, Section 10.11
141 * @param device PCI device
142 * @param vector interrupt vector.
145 pci_setup_msi(struct pci_device* device, int vector);
147 #endif /* __LUNAIX_PCI_H */