1 #include <arch/x86/idt.h>
2 #include <arch/x86/interrupts.h>
7 uint64_t _idt[IDT_ENTRY];
8 uint16_t _idt_limit = sizeof(_idt) - 1;
11 _set_idt_entry(uint32_t vector,
12 uint16_t seg_selector,
17 uintptr_t offset = (uintptr_t)isr;
18 _idt[vector] = (offset & 0xffff0000) | IDT_ATTR(dpl, type);
20 _idt[vector] |= (seg_selector << 16) | (offset & 0x0000ffff);
24 _set_idt_intr_entry(uint32_t vector,
25 uint16_t seg_selector,
29 _set_idt_entry(vector, seg_selector, isr, dpl, IDT_INTERRUPT);
33 _set_idt_trap_entry(uint32_t vector,
34 uint16_t seg_selector,
38 _set_idt_entry(vector, seg_selector, isr, dpl, IDT_TRAP);
44 // CPU defined interrupts
45 _set_idt_intr_entry(FAULT_DIVISION_ERROR, 0x08, _asm_isr0, 0);
46 _set_idt_intr_entry(FAULT_GENERAL_PROTECTION, 0x08, _asm_isr13, 0);
47 _set_idt_intr_entry(FAULT_PAGE_FAULT, 0x08, _asm_isr14, 0);
49 _set_idt_intr_entry(APIC_ERROR_IV, 0x08, _asm_isr250, 0);
50 _set_idt_intr_entry(APIC_LINT0_IV, 0x08, _asm_isr251, 0);
51 _set_idt_intr_entry(APIC_SPIV_IV, 0x08, _asm_isr252, 0);
52 _set_idt_intr_entry(APIC_TIMER_IV, 0x08, _asm_isr253, 0);
53 _set_idt_intr_entry(PC_KBD_IV, 0x08, _asm_isr201, 0);
55 _set_idt_intr_entry(RTC_TIMER_IV, 0x08, _asm_isr210, 0);
57 // system defined interrupts
58 _set_idt_intr_entry(LUNAIX_SYS_PANIC, 0x08, _asm_isr32, 0);
60 // syscall is a trap gate (recall: trap does NOT clear IF flag upon
62 // // XXX: this should be fine, as our design of context switch support
63 // interruptible syscall We make this a non-trap entry, and enable interrupt
65 // FIXME: This may cause nasty concurrency bug! We should 'lockify' our
67 _set_idt_intr_entry(LUNAIX_SYS_CALL, 0x08, _asm_isr33, 3);