move msi-related functionality to generic isrm

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index e5bbd456285db9aa36e32a64d562074003ddc136..95ed7fd313eb0bc885507e2ca0ae290ca18b2d59 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -6,8 +6,10 @@
 #include <lunaix/ds/llist.h>
 #include <lunaix/types.h>
 
 #include <lunaix/ds/llist.h>
 #include <lunaix/types.h>
 

-#define EXPORT_PCI_DEVICE(id, pci_devdef)                                      \
-    EXPORT_DEVICE(id, &(pci_devdef)->devdef, load_pci_probe)
+#include <asm-generic/isrm.h>
+
+#define EXPORT_PCI_DEVICE(id, pci_devdef, stage)                               \
+    EXPORT_DEVICE(id, &(pci_devdef)->devdef, stage)

 
 #define PCI_MATCH_EXACT -1
 #define PCI_MATCH_ANY 0
 
 #define PCI_MATCH_EXACT -1
 #define PCI_MATCH_ANY 0


@@ -38,8 +40,10 @@
 #define PCI_BAR_TYPE(x) ((x) & 0x6)
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 #define PCI_BAR_TYPE(x) ((x) & 0x6)
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)

+#define PCI_BAR_COUNT 6

 
 

-#define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_LO(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_HI(msi_base) ((msi_base) + 8)

 #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
 #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
 
 #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
 #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
 


@@ -102,6 +106,12 @@ struct pci_device
 };
 #define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))
 
 };
 #define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))
 

+struct pci_device_list
+{
+    struct llist_header peers;
+    struct pci_device* pcidev;
+};
+

 typedef void* (*pci_drv_init)(struct pci_device*);
 
 #define PCI_DEVIDENT(vendor, id)                                               \
 typedef void* (*pci_drv_init)(struct pci_device*);
 
 #define PCI_DEVIDENT(vendor, id)                                               \


@@ -109,11 +119,14 @@ typedef void* (*pci_drv_init)(struct pci_device*);
 
 struct pci_device_def
 {
 
 struct pci_device_def
 {

-    u32_t dev_class;
-    u32_t dev_ident;
-    u32_t ident_mask;

     struct device_def devdef;
     struct device_def devdef;

+
+    bool (*test_compatibility)(struct pci_device_def*, struct pci_device*);

 };
 };

+#define pcidev_def(dev_def_ptr)                                                \
+    container_of((dev_def_ptr), struct pci_device_def, devdef)
+
+#define binded_pcidev(pcidev) ((pcidev)->binding.def)

 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备


@@ -158,7 +171,98 @@ pci_bind_instance(struct pci_device* pcidev, void* devobj);
 void
 pci_probe_bar_info(struct pci_device* device);
 
 void
 pci_probe_bar_info(struct pci_device* device);
 

+void
+pci_setup_msi(struct pci_device* device, msi_vector_t msiv);
+

 void
 pci_probe_msi_info(struct pci_device* device);
 
 void
 pci_probe_msi_info(struct pci_device* device);
 

+int
+pci_bind_definition(struct pci_device_def* pcidev_def, bool* more);
+
+int
+pci_bind_definition_all(struct pci_device_def* pcidef);
+
+static inline unsigned int
+pci_device_vendor(struct pci_device* pcidev)
+{
+    return PCI_DEV_VENDOR(pcidev->device_info);
+}
+
+static inline unsigned int
+pci_device_devid(struct pci_device* pcidev)
+{
+    return PCI_DEV_DEVID(pcidev->device_info);
+}
+
+static inline unsigned int
+pci_device_class(struct pci_device* pcidev)
+{
+    return PCI_DEV_CLASS(pcidev->class_info);
+}
+
+static inline struct pci_base_addr*
+pci_device_bar(struct pci_device* pcidev, int index)
+{
+    return &pcidev->bar[index];
+}
+
+static inline void
+pci_cmd_set_mmio(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_MM_ACCESS;
+}
+
+
+static inline void
+pci_cmd_set_pmio(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_IO_ACCESS;
+}
+
+static inline void
+pci_cmd_set_msi(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_DISABLE_INTR;
+}
+
+static inline void
+pci_cmd_set_bus_master(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_BUS_MASTER;
+}
+
+static inline void
+pci_cmd_set_fast_b2b(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_FAST_B2B;
+}
+
+static inline bool
+pci_bar_mmio_space(struct pci_base_addr* bar)
+{
+    return (bar->type & BAR_TYPE_MMIO);
+}
+
+static inline bool
+pci_capability_msi(struct pci_device* pcidev)
+{
+    return !!pcidev->msi_loc;
+}
+
+static inline int
+pci_intr_irq(struct pci_device* pcidev)
+{
+    return PCI_INTR_IRQ(pcidev->intr_info);
+}
+
+void
+pci_apply_command(struct pci_device* pcidev, pci_reg_t cmd);
+
+pci_reg_t
+pci_read_cspace(ptr_t base, int offset);
+
+void
+pci_write_cspace(ptr_t base, int offset, pci_reg_t data);
+

 #endif /* __LUNAIX_PCI_H */
 #endif /* __LUNAIX_PCI_H */