#include <lunaix/types.h>
#include <lunaix/hart_state.h>
+#include <hal/devtree.h>
+
typedef void (*isr_cb)(const struct hart_state*);
+typedef struct {
+ ptr_t msi_addr;
+ reg_t msi_data;
+ int mapped_iv;
+} msi_vector_t;
+#define msi_addr(msiv) ((msiv).msi_addr)
+#define msi_data(msiv) ((msiv).msi_data)
+#define msi_vect(msiv) ((msiv).mapped_iv)
+
void
isrm_init();
isrm_ivexalloc(isr_cb handler);
/**
- * @brief Bind a given irq and associated handler to an iv
+ * @brief Allocate an iv resource for MSI use
*
- * @param iv iv allocated by system
+ * @param iv
*/
-int
-isrm_bindirq(int irq, isr_cb irq_handler);
+msi_vector_t
+isrm_msialloc(isr_cb handler);
/**
- * @brief Bind given iv with it's associated handler
+ * @brief Bind the iv according to given device tree node
*
- * @param iv
- * @param handler
+ * @param node
*/
-void
-isrm_bindiv(int iv, isr_cb handler);
+int
+isrm_bind_dtnode(struct dt_intr_node* node);
/**
* @brief Get the handler associated with the given iv
void
isrm_set_payload(int iv, ptr_t);
-void
-isrm_irq_attach(int irq, int iv, cpu_t dest, u32_t flags);
-
/**
* @brief Notify end of interrupt event
*
#include <hal/hwtimer.h>
-#include <asm-generic/isrm.h>
#include <lunaix/spike.h>
#include <lunaix/process.h>
+#include <asm/x86_isrm.h>
+
#include "asm/x86.h"
#include "asm/hart.h"
#include <asm/hart.h>
#include "asm/x86.h"
-#include <asm-generic/isrm.h>
-
#include <lunaix/mm/vmm.h>
#include <lunaix/process.h>
#include <lunaix/sched.h>
#include <lunaix/syslog.h>
+#include <asm/x86_isrm.h>
+
LOG_MODULE("INTR")
static inline void
#include <asm/hart.h>
-#include <asm-generic/isrm.h>
#include <lunaix/process.h>
#include <lunaix/sched.h>
#include <lunaix/spike.h>
#include <klibc/strfmt.h>
+#include <asm/x86_isrm.h>
#include "asm/soc/apic.h"
#include "asm/x86.h"
#include <lunaix/spike.h>
#include <lunaix/owloysius.h>
-#include <asm-generic/isrm.h>
+#include <asm/x86_isrm.h>
#include "asm/x86.h"
#include "asm/soc/ioapic.h"
isrm_notify_eoi(id, LUNAIX_SCHED);
}
+msi_vector_t
+isrm_msialloc(isr_cb handler)
+{
+ unsigned int iv = isrm_ivexalloc(handler);
+
+ return (msi_vector_t){
+ .msi_addr = 0xfee00000,
+ .msi_data = iv,
+ .mapped_iv = iv
+ };
+}
+
+int
+isrm_bind_dtnode(struct dt_intr_node* node)
+{
+ fail("not supported");
+}
+
static void
__intc_init()
#include <lunaix/clock.h>
#include <lunaix/compiler.h>
-#include <asm-generic/isrm.h>
#include <lunaix/spike.h>
#include <lunaix/syslog.h>
+#include <asm/x86_isrm.h>
#include "asm/soc/apic.h"
LOG_MODULE("APIC_TIMER")
*
*/
-#include <asm-generic/isrm.h>
#include <lunaix/mm/valloc.h>
#include <lunaix/status.h>
#include <lunaix/hart_state.h>
#include <klibc/string.h>
+#include <asm/x86_isrm.h>
#include <asm/x86_pmio.h>
#define RTC_INDEX_PORT 0x70
port_wrdword(PCI_CONFIG_DATA, data);
}
-#endif
-
-u16_t
-pci_config_msi_data(int vector) {
- return vector;
-}
-
-ptr_t
-pci_get_msi_base() {
- return 0xFEE00000;
-}
-
+#endif
\ No newline at end of file
#include <lunaix/clock.h>
#include <lunaix/ds/mutex.h>
#include <lunaix/input.h>
-#include <asm-generic/isrm.h>
#include <lunaix/keyboard.h>
#include <lunaix/syslog.h>
#include <lunaix/timer.h>
#include <klibc/string.h>
#include "asm/x86_cpu.h"
+#include <asm/x86_isrm.h>
#include <asm/x86_pmio.h>
#define PS2_PORT_ENC_DATA 0x60
--- /dev/null
+#ifndef __LUNAIX_X86_ISRM_H
+#define __LUNAIX_X86_ISRM_H
+
+#include <asm-generic/isrm.h>
+
+/**
+ * @brief Bind a given irq and associated handler to an iv
+ *
+ * @param iv iv allocated by system
+ */
+int
+isrm_bindirq(int irq, isr_cb irq_handler);
+
+/**
+ * @brief Bind given iv with it's associated handler
+ *
+ * @param iv
+ * @param handler
+ */
+void
+isrm_bindiv(int iv, isr_cb handler);
+
+void
+isrm_irq_attach(int irq, int iv, cpu_t dest, u32_t flags);
+
+
+#endif /* __LUNAIX_X86_ISRM_H */
struct pci_device* ahci_dev;
struct pci_base_addr* bar6;
struct ahci_driver* ahci_drv;
+ msi_vector_t msiv;
ahci_dev = PCI_DEVICE(dev);
bar6 = pci_device_bar(ahci_dev, 5);
pci_cmd_set_mmio(&cmd);
pci_cmd_set_msi(&cmd);
pci_apply_command(ahci_dev, cmd);
+
+ assert(pci_capability_msi(ahci_dev));
- int iv;
- if (pci_capability_msi(ahci_dev)) {
- iv = isrm_ivexalloc(ahci_hba_isr);
- pci_setup_msi(ahci_dev, iv);
- }
- else {
- iv = pci_intr_irq(ahci_dev);
- iv = isrm_bindirq(iv, ahci_hba_isr);
- }
+ msiv = isrm_msialloc(ahci_hba_isr);
+ pci_setup_msi(ahci_dev, msiv);
struct ahci_driver_param param = {
.mmio_base = bar6->start,
.mmio_size = bar6->size,
- .ahci_iv = iv,
+ .ahci_iv = msi_vect(msiv),
};
ahci_drv = ahci_driver_init(¶m);
}
void
-pci_setup_msi(struct pci_device* device, int vector)
+pci_setup_msi(struct pci_device* device, msi_vector_t msiv)
{
// PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
- ptr_t msi_addr = pci_get_msi_base();
- u32_t msi_data = pci_config_msi_data(vector);
+ ptr_t msi_addr = msi_addr(msiv);
+ u32_t msi_data = msi_data(msiv);
pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
pci_reg_t msg_ctl = reg1 >> 16;
#include <lunaix/device.h>
-#include <asm-generic/isrm.h>
#include <lunaix/syslog.h>
#include <asm/x86_pmio.h>
+#include <asm/x86_isrm.h>
#include "16x50.h"
static struct device_def uart_pmio_def = {
.class = DEVCLASS(DEVIF_SOC, DEVFN_CHAR, DEV_UART16550),
- .name = "16550 UART (PIO)",
+ .name = "16550 UART (pmio, isa-bus)",
.init = upiom_init
};
EXPORT_DEVICE(uart16550_pmio, &uart_pmio_def, load_onboot);
\ No newline at end of file
static int
pci16650_binder(struct device_def* def, struct device* dev)
{
- int irq;
struct pci_base_addr* bar;
struct pci_device* pcidev;
struct uart16550* uart;
struct serial_dev* sdev;
+ msi_vector_t msiv;
pcidev = PCI_DEVICE(dev);
if (bar->size == 0) {
continue;
}
-
+
if (!pci_bar_mmio_space(bar)) {
+#ifdef CONFIG_PCI_PMIO
pci_cmd_set_pmio(&cmd);
pci_apply_command(pcidev, cmd);
uart = uart16x50_pmio_create(bar->start);
- }
- else {
+#else
+ WARN("plaform configured to not support pmio access.")
+ continue;
+#endif
+ } else
+ {
pci_cmd_set_mmio(&cmd);
pci_apply_command(pcidev, cmd);
continue;
}
- if (pci_capability_msi(pcidev)) {
- irq = isrm_ivexalloc(uart_msi_irq_handler);
- isrm_set_payload(irq, __ptr(uart));
- pci_setup_msi(pcidev, irq);
- }
- else {
- irq = pci_intr_irq(pcidev);
- irq = isrm_bindirq(irq, uart_intx_irq_handler);
+ if (!pci_capability_msi(pcidev)) {
+ WARN("failed to fallback to legacy INTx: not supported.");
+ continue;
}
+ msiv = isrm_msialloc(uart_msi_irq_handler);
+ isrm_set_payload(msi_vect(msiv), __ptr(uart));
+ pci_setup_msi(pcidev, msiv);
+
INFO("base: 0x%x (%s), irq=%d (%s)",
bar->start,
pci_bar_mmio_space(bar) ? "mmio" : "pmio",
- irq,
+ msi_vect(msiv),
pci_capability_msi(pcidev) ? "msi" : "intx, re-routed");
- uart->iv = irq;
+ uart->iv = msi_vect(msiv);
sdev = uart_create_serial(uart, &def->class, &pci_ports, "PCI");
pci_bind_instance(pcidev, sdev);
type(bool)
+ default(True)
+
is_x86 = v(arch) in ["i386", "x86_64"]
- default(is_x86)
+ if not is_x86:
+ set_value(False)
return is_x86
#include <lunaix/ds/llist.h>
#include <lunaix/types.h>
+#include <asm-generic/isrm.h>
+
#define EXPORT_PCI_DEVICE(id, pci_devdef, stage) \
EXPORT_DEVICE(id, &(pci_devdef)->devdef, stage)
pci_probe_bar_info(struct pci_device* device);
void
-pci_setup_msi(struct pci_device* device, int vector);
+pci_setup_msi(struct pci_device* device, msi_vector_t msiv);
void
pci_probe_msi_info(struct pci_device* device);
void
pci_write_cspace(ptr_t base, int offset, pci_reg_t data);
-u16_t
-pci_config_msi_data(int vector);
-
-ptr_t
-pci_get_msi_base();
-
-
#endif /* __LUNAIX_PCI_H */
return status;
}
+ if (!elf_check_arch(elf)) {
+ return EINVAL;
+ }
+
if ((status = elf_read_phdr(elf)) < 0) {
elf_close(elf);
return status;
goto done;
}
- if (!elf_check_arch(&elf)) {
- errno = EINVAL;
- goto done;
- }
-
if (!(elf_check_exec(&elf, ET_EXEC) || elf_check_exec(&elf, ET_DYN))) {
errno = ENOEXEC;
goto done;
.NOTPARALLEL:
export KCMD=$(CMDLINE)
export LBUILD ARCH MODE
-all: $(kbuild_dir) tool kernel usr/build
+all: $(kbuild_dir) tool kernel
rootfs: usr/build
$(call status,TASK,$(notdir $@))