regression: test serial port r/w.
authorMinep <lunaixsky@qq.com>
Tue, 5 Sep 2023 23:50:17 +0000 (00:50 +0100)
committerMinep <lunaixsky@qq.com>
Tue, 5 Sep 2023 23:51:17 +0000 (00:51 +0100)
fix: uart register bitmap
fix: refine context switch trace message
feat: add a dedicated program to host all test routines


No differences found