// 对低1MiB空间进行对等映射（Identity
// mapping），也包括了我们的VGA，方便内核操作。
- for (uint32_t i = 0; i < 256; i++) {
+ for (u32_t i = 0; i < 256; i++) {
SET_PTE(ptd,
PG_TABLE_IDENTITY,
i,
// 对等映射我们的hhk_init，这样一来，当分页与地址转换开启后，我们依然能够照常执行最终的
// jmp 指令来跳转至
// 内核的入口点
- for (uint32_t i = 0; i < HHK_PAGE_COUNT; i++) {
+ for (u32_t i = 0; i < HHK_PAGE_COUNT; i++) {
SET_PTE(ptd,
PG_TABLE_IDENTITY,
256 + i,
// 这里是一些计算，主要是计算应当映射进的 页目录 与 页表 的条目索引（Entry
// Index）
- uint32_t kernel_pde_index = L1_INDEX(sym_val(__kernel_start));
- uint32_t kernel_pte_index = L2_INDEX(sym_val(__kernel_start));
- uint32_t kernel_pg_counts = KERNEL_PAGE_COUNT;
+ u32_t kernel_pde_index = L1_INDEX(sym_val(__kernel_start));
+ u32_t kernel_pte_index = L2_INDEX(sym_val(__kernel_start));
+ u32_t kernel_pg_counts = KERNEL_PAGE_COUNT;
// 将内核所需要的页表注册进页目录
// 当然，就现在而言，我们的内核只占用不到50个页（每个页表包含1024个页）
// 这里分配了3个页表（12MiB），未雨绸缪。
- for (uint32_t i = 0; i < PG_TABLE_STACK - PG_TABLE_KERNEL; i++) {
+ for (u32_t i = 0; i < PG_TABLE_STACK - PG_TABLE_KERNEL; i++) {
SET_PDE(ptd,
kernel_pde_index + i,
NEW_L1_ENTRY(PG_PREM_URW, PT_ADDR(ptd, PG_TABLE_KERNEL + i)))
uintptr_t kernel_pm = V2P(&__kernel_start);
// 重映射内核至高半区地址（>=0xC0000000）
- for (uint32_t i = 0; i < kernel_pg_counts; i++) {
+ for (u32_t i = 0; i < kernel_pg_counts; i++) {
// FIXME: 只是用作用户模式（R3）测试！
// 在实际中，内核代码除了极少部分需要暴露给R3（如从信号返回），其余的应为R0。
SET_PTE(ptd,
SET_PDE(ptd, PG_MAX_ENTRIES - 1, NEW_L1_ENTRY(T_SELF_REF_PERM, ptd));
}
-uint32_t
+u32_t
__save_subset(uint8_t* destination, uint8_t* base, unsigned int size)
{
unsigned int i = 0;
void
_save_multiboot_info(multiboot_info_t* info, uint8_t* destination)
{
- uint32_t current = 0;
+ u32_t current = 0;
uint8_t* info_b = (uint8_t*)info;
for (; current < sizeof(multiboot_info_t); current++) {
*(destination + current) = *(info_b + current);
}
void
-_hhk_init(ptd_t* ptd, uint32_t kpg_size)
+_hhk_init(ptd_t* ptd, u32_t kpg_size)
{
// 初始化 kpg 全为0
// P.s. 真没想到GRUB会在这里留下一堆垃圾！ 老子的页表全乱套了！
uint8_t* kpg = (uint8_t*)ptd;
- for (uint32_t i = 0; i < kpg_size; i++) {
+ for (u32_t i = 0; i < kpg_size; i++) {
*(kpg + i) = 0;
}
uint8_t* mem_start = entry.addr_low & ~0xf;
size_t len = entry.len_low;
for (size_t j = 0; j < len; j += 16) {
- uint32_t sig_low = *((uint32_t*)(mem_start + j));
- // uint32_t sig_high = *((uint32_t*)(mem_start+j) + 1);
+ u32_t sig_low = *((u32_t*)(mem_start + j));
+ // u32_t sig_high = *((u32_t*)(mem_start+j) + 1);
if (sig_low == ACPI_RSDP_SIG_L) {
rsdp = (acpi_rsdp_t*)(mem_start + j);
break;
// You know what, I just search the entire 1MiB for Celestia's sake.
uint8_t* mem_start = 0x4000;
for (; mem_start < 0x100000; mem_start += 16) {
- uint32_t sig_low = *((uint32_t*)(mem_start));
+ u32_t sig_low = *((u32_t*)(mem_start));
// XXX: do we need to compare this as well?
- // uint32_t sig_high = *((uint32_t*)(mem_start+j) + 1);
+ // u32_t sig_high = *((u32_t*)(mem_start+j) + 1);
if (sig_low == ACPI_RSDP_SIG_L) {
rsdp = (acpi_rsdp_t*)(mem_start);
break;
i,
hbadev->model,
hbadev->block_size,
- (uint32_t)hbadev->max_lba);
+ (u32_t)hbadev->max_lba);
ahci_register_device(hbadev);
}
hba_reg_t pxsact = port->regs[HBA_RPxSACT];
hba_reg_t pxci = port->regs[HBA_RPxCI];
hba_reg_t free_bmp = pxsact | pxci;
- uint32_t i = 0;
+ u32_t i = 0;
for (; i <= port->hba->cmd_slots && (free_bmp & 0x1); i++, free_bmp >>= 1)
;
return i | -(i > port->hba->cmd_slots);
goto fail;
}
- scsi_parse_capacity(port->device, (uint32_t*)data_in);
+ scsi_parse_capacity(port->device, (u32_t*)data_in);
done:
// reset interrupt status and unmask D2HR interrupt
void
sata_read_error(struct hba_port* port)
{
- uint32_t tfd = port->regs[HBA_RPxTFD];
+ u32_t tfd = port->regs[HBA_RPxTFD];
port->device->last_result.sense_key = (tfd & 0xf000) >> 12;
port->device->last_result.error = (tfd & 0x0f00) >> 8;
port->device->last_result.status = tfd & 0x00ff;
void
scsi_create_packet12(struct scsi_cdb12* cdb,
uint8_t opcode,
- uint32_t lba,
- uint32_t alloc_size)
+ u32_t lba,
+ u32_t alloc_size)
{
memset(cdb, 0, sizeof(*cdb));
cdb->opcode = opcode;
scsi_create_packet16(struct scsi_cdb16* cdb,
uint8_t opcode,
uint64_t lba,
- uint32_t alloc_size)
+ u32_t alloc_size)
{
memset(cdb, 0, sizeof(*cdb));
cdb->opcode = opcode;
- cdb->lba_be_hi = SCSI_FLIP((uint32_t)(lba >> 32));
- cdb->lba_be_lo = SCSI_FLIP((uint32_t)lba);
+ cdb->lba_be_hi = SCSI_FLIP((u32_t)(lba >> 32));
+ cdb->lba_be_lo = SCSI_FLIP((u32_t)lba);
cdb->length = SCSI_FLIP(alloc_size);
}
void
-scsi_parse_capacity(struct hba_device* device, uint32_t* parameter)
+scsi_parse_capacity(struct hba_device* device, u32_t* parameter)
{
if (device->cbd_size == SCSI_CDB16) {
device->max_lba =
header->options |= (HBA_CMDH_WRITE * (write == 1)) | HBA_CMDH_ATAPI;
size_t size = vbuf_size(io_req->vbuf);
- uint32_t count = ICEIL(size, port->device->block_size);
+ u32_t count = ICEIL(size, port->device->block_size);
struct sata_reg_fis* fis = (struct sata_reg_fis*)table->command_fis;
void* cdb = table->atapi_cmd;
__blk_rd_wwid(struct twimap* map)
{
struct hba_device* hbadev = twimap_data(map, struct hba_device*);
- uint32_t h = hbadev->wwn >> 32;
- uint32_t l = (uint32_t)hbadev->wwn;
+ u32_t h = hbadev->wwn >> 32;
+ u32_t l = (u32_t)hbadev->wwn;
if ((h | l)) {
twimap_printf(map, "wwn:%x%x", h, l);
} else {
#define IDDEV_OFFLPP 106
#define IDDEV_OFFCAPABILITIES 49
-static uint32_t cdb_size[] = { SCSI_CDB12, SCSI_CDB16, 0, 0 };
+static u32_t cdb_size[] = { SCSI_CDB12, SCSI_CDB16, 0, 0 };
void
ahci_parse_dev_info(struct hba_device* dev_info, uint16_t* data)
{
- dev_info->max_lba = *((uint32_t*)(data + IDDEV_OFFMAXLBA));
- dev_info->block_size = *((uint32_t*)(data + IDDEV_OFFLSECSIZE));
+ dev_info->max_lba = *((u32_t*)(data + IDDEV_OFFMAXLBA));
+ dev_info->block_size = *((u32_t*)(data + IDDEV_OFFLSECSIZE));
dev_info->cbd_size = cdb_size[(*data & 0x3)];
dev_info->wwn = *(uint64_t*)(data + IDDEV_OFFWWN);
dev_info->block_per_sec = 1 << (*(data + IDDEV_OFFLPP) & 0xf);
dev_info->alignment_offset = *(data + IDDEV_OFFALIGN) & 0x3fff;
- dev_info->capabilities = *((uint32_t*)(data + IDDEV_OFFCAPABILITIES));
+ dev_info->capabilities = *((u32_t*)(data + IDDEV_OFFCAPABILITIES));
if (!dev_info->block_size) {
dev_info->block_size = 512;
: "eax", "ecx", "edx");
// Print the basic information of our current local APIC
- uint32_t apic_id = apic_read_reg(APIC_IDR) >> 24;
- uint32_t apic_ver = apic_read_reg(APIC_VER);
+ u32_t apic_id = apic_read_reg(APIC_IDR) >> 24;
+ u32_t apic_ver = apic_read_reg(APIC_VER);
kprintf(KINFO "ID: %x, Version: %x, Max LVT: %u\n",
apic_id,
apic_write_reg(APIC_TPR, APIC_PRIORITY(2, 0));
// enable APIC
- uint32_t spiv = apic_read_reg(APIC_SPIVR);
+ u32_t spiv = apic_read_reg(APIC_SPIVR);
// install our handler for spurious interrupt.
spiv = (spiv & ~0xff) | APIC_SPIV_APIC_ENABLE | APIC_SPIV_IV;
+#include <cpuid.h>
#include <hal/cpu.h>
#include <stdint.h>
-#include <cpuid.h>
-void cpu_get_model(char* model_out) {
- uint32_t* out = (uint32_t*)model_out;
+void
+cpu_get_model(char* model_out)
+{
+ u32_t* out = (u32_t*)model_out;
reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
-
+
__get_cpuid(0, &eax, &ebx, &ecx, &edx);
out[0] = ebx;
#define BRAND_LEAF 0x80000000UL
-int cpu_brand_string_supported() {
+int
+cpu_brand_string_supported()
+{
reg32 supported = __get_cpuid_max(BRAND_LEAF, 0);
return (supported >= 0x80000004UL);
}
-void cpu_get_brand(char* brand_out) {
- if(!cpu_brand_string_supported()) {
+void
+cpu_get_brand(char* brand_out)
+{
+ if (!cpu_brand_string_supported()) {
brand_out[0] = '?';
brand_out[1] = '\0';
}
- uint32_t* out = (uint32_t*) brand_out;
+ u32_t* out = (u32_t*)brand_out;
reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
- for (uint32_t i = 2, j = 0; i < 5; i++)
- {
+ for (u32_t i = 2, j = 0; i < 5; i++) {
__get_cpuid(BRAND_LEAF + i, &eax, &ebx, &ecx, &edx);
out[j] = eax;
out[j + 1] = ebx;
out[j + 2] = ecx;
out[j + 3] = edx;
- j+=4;
+ j += 4;
}
brand_out[48] = '\0';
}
-
int
-cpu_has_apic() {
+cpu_has_apic()
+{
// reference: Intel manual, section 10.4.2
reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
__get_cpuid(1, &eax, &ebx, &ecx, &edx);
-
+
return (edx & 0x100);
}
void
-cpu_rdmsr(uint32_t msr_idx, uint32_t* reg_high, uint32_t* reg_low)
+cpu_rdmsr(u32_t msr_idx, u32_t* reg_high, u32_t* reg_low)
{
- uint32_t h = 0, l = 0;
+ u32_t h = 0, l = 0;
asm volatile("rdmsr" : "=d"(h), "=a"(l) : "c"(msr_idx));
*reg_high = h;
}
void
-cpu_wrmsr(uint32_t msr_idx, uint32_t reg_high, uint32_t reg_low)
+cpu_wrmsr(u32_t msr_idx, u32_t reg_high, u32_t reg_low)
{
asm volatile("wrmsr" : : "d"(reg_high), "a"(reg_low), "c"(msr_idx));
}
\ No newline at end of file
#include <lunaix/common.h>
#include <lunaix/mm/mmio.h>
-#define IOAPIC_REG_SEL *((volatile uint32_t*)(_ioapic_base + IOAPIC_IOREGSEL))
-#define IOAPIC_REG_WIN *((volatile uint32_t*)(_ioapic_base + IOAPIC_IOWIN))
+#define IOAPIC_REG_SEL *((volatile u32_t*)(_ioapic_base + IOAPIC_IOREGSEL))
+#define IOAPIC_REG_WIN *((volatile u32_t*)(_ioapic_base + IOAPIC_IOWIN))
static volatile uintptr_t _ioapic_base;
}
void
-ioapic_write(uint8_t sel, uint32_t val)
+ioapic_write(uint8_t sel, u32_t val)
{
IOAPIC_REG_SEL = sel;
IOAPIC_REG_WIN = val;
}
-uint32_t
+u32_t
ioapic_read(uint8_t sel)
{
IOAPIC_REG_SEL = sel;
}
void
-ioapic_redirect(uint8_t irq, uint8_t vector, uint8_t dest, uint32_t flags)
+ioapic_redirect(uint8_t irq, uint8_t vector, uint8_t dest, u32_t flags)
{
uint8_t reg_sel = IOAPIC_IOREDTBL_BASE + irq * 2;
void
pci_probe_device(int bus, int dev, int funct)
{
- uint32_t base = PCI_ADDRESS(bus, dev, funct);
+ u32_t base = PCI_ADDRESS(bus, dev, funct);
pci_reg_t reg1 = pci_read_cspace(base, 0);
// Vendor=0xffff则表示设备不存在
void
pci_probe_bar_info(struct pci_device* device)
{
- uint32_t bar;
+ u32_t bar;
struct pci_base_addr* ba;
for (size_t i = 0; i < 6; i++) {
ba = &device->bar[i];
}
pci_reg_t cap_ptr = pci_read_cspace(device->cspace_base, 0x34) & 0xff;
- uint32_t cap_hdr;
+ u32_t cap_hdr;
while (cap_ptr) {
cap_hdr = pci_read_cspace(device->cspace_base, cap_ptr);
}
size_t
-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num)
{
pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num));
if (!bar) {
pci_setup_msi(struct pci_device* device, int vector)
{
// Dest: APIC#0, Physical Destination, No redirection
- uint32_t msi_addr = (__APIC_BASE_PADDR);
+ u32_t msi_addr = (__APIC_BASE_PADDR);
// Edge trigger, Fixed delivery
- uint32_t msi_data = vector;
+ u32_t msi_data = vector;
pci_write_cspace(
device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
struct pci_device*
pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId)
{
- uint32_t dev_info = vendorId | (deviceId << 16);
+ u32_t dev_info = vendorId | (deviceId << 16);
struct pci_device *pos, *n;
llist_for_each(pos, n, &pci_devices, dev_chain)
{
}
struct pci_device*
-pci_get_device_by_class(uint32_t class)
+pci_get_device_by_class(u32_t class)
{
struct pci_device *pos, *n;
llist_for_each(pos, n, &pci_devices, dev_chain)
#ifndef __LUNAIX_TSS_H
#define __LUNAIX_TSS_H
-#include <stdint.h>
+#include <lunaix/types.h>
-struct x86_tss {
- uint32_t link;
- uint32_t esp0;
+struct x86_tss
+{
+ u32_t link;
+ u32_t esp0;
uint16_t ss0;
uint8_t __padding[94];
} __attribute__((packed));
-void tss_update_esp(uint32_t esp0);
-
+void
+tss_update_esp(u32_t esp0);
+
#endif /* __LUNAIX_TSS_H */
typedef struct
{
- uint32_t signature_l;
- uint32_t signature_h;
+ u32_t signature_l;
+ u32_t signature_h;
uint8_t chksum;
char oem_id[6];
// Revision
uint8_t rev;
acpi_rsdt_t* rsdt;
- uint32_t length;
+ u32_t length;
acpi_sdthdr_t* xsdt;
uint8_t x_chksum;
char reserved[3]; // Reserved field
// Pulled from ACPI Specification (v6.4) section 5.2.9
-enum PMProfile {
+enum PMProfile
+{
Desktop = 1,
Mobile = 2,
Workstation = 3,
#define ITIME_MON_ALARM 1
#define ITIME_CENTURY 2
-#define IAPC_ARCH_LEGACY 0x1
-#define IAPC_ARCH_8042 0x2
-#define IAPC_ARCH_NO_VGA 0x4
-#define IAPC_ARCH_NO_MSI 0x8
-#define IAPC_ARCH_ASPM 0x10
-#define IAPC_ARCH_NO_RTC 0x20
+#define IAPC_ARCH_LEGACY 0x1
+#define IAPC_ARCH_8042 0x2
+#define IAPC_ARCH_NO_VGA 0x4
+#define IAPC_ARCH_NO_MSI 0x8
+#define IAPC_ARCH_ASPM 0x10
+#define IAPC_ARCH_NO_RTC 0x20
-typedef struct acpi_fadt {
+typedef struct acpi_fadt
+{
acpi_sdthdr_t header;
- uint32_t firmware_controller_addr;
- uint32_t dsdt_addr;
+ u32_t firmware_controller_addr;
+ u32_t dsdt_addr;
uint8_t reserved;
uint8_t pm_profile;
uint16_t sci_int;
- uint32_t smi_cmd_port_addr;
+ u32_t smi_cmd_port_addr;
uint8_t smi_acpi_enable;
uint8_t smi_acpi_disable;
uint8_t smi_s4bios_state;
uint8_t smi_pstate;
- uint32_t pm_reg_ports[6];
- uint32_t gpe0_port_addr;
- uint32_t gpe1_port_addr;
+ u32_t pm_reg_ports[6];
+ u32_t gpe0_port_addr;
+ u32_t gpe1_port_addr;
uint8_t pm_reg_lens[4];
uint8_t gpe0_len;
uint8_t gpe1_len;
acpi_ics_hdr_t header;
uint8_t processor_id;
uint8_t apic_id;
- uint32_t flags;
+ u32_t flags;
} ACPI_TABLE_PACKED acpi_apic_t;
/**
acpi_ics_hdr_t header;
uint8_t ioapic_id;
uint8_t reserved;
- uint32_t ioapic_addr;
- // The global system interrupt offset for this IOAPIC. (Kind of IRQ offset for a slave IOAPIC)
- uint32_t gis_offset;
+ u32_t ioapic_addr;
+ // The global system interrupt offset for this IOAPIC. (Kind of IRQ offset
+ // for a slave IOAPIC)
+ u32_t gis_offset;
} ACPI_TABLE_PACKED acpi_ioapic_t;
/**
// PIC
uint8_t source;
// global system interrupt. The override of source in APIC mode
- uint32_t gsi;
+ u32_t gsi;
uint16_t flags;
} ACPI_TABLE_PACKED acpi_intso_t;
{
acpi_sdthdr_t header;
void* apic_addr;
- uint32_t flags;
+ u32_t flags;
// Here is a bunch of packed ICS reside here back-to-back.
} ACPI_TABLE_PACKED acpi_madt_t;
struct acpi_mcfg_alloc
{
- uint32_t base_addr_lo;
- uint32_t base_addr_hi;
+ u32_t base_addr_lo;
+ u32_t base_addr_hi;
uint16_t pci_seg_num;
uint8_t pci_bus_start;
uint8_t pci_bus_end;
- uint32_t reserve;
+ u32_t reserve;
} ACPI_TABLE_PACKED;
struct mcfg_alloc_info
{
- uint32_t base_addr;
+ u32_t base_addr;
uint16_t pci_seg_num;
uint8_t pci_bus_start;
uint8_t pci_bus_end;
#ifndef __LUNAIX_ACPI_SDT_H
#define __LUNAIX_ACPI_SDT_H
-#include <stdint.h>
+#include <lunaix/types.h>
-#define ACPI_TABLE_PACKED __attribute__((packed))
+#define ACPI_TABLE_PACKED __attribute__((packed))
typedef struct acpi_sdthdr
{
- uint32_t signature;
- uint32_t length;
+ u32_t signature;
+ u32_t length;
// Revision
uint8_t rev;
uint8_t chksum;
char oem_id[6];
char oem_table_id[8];
- uint32_t oem_rev;
- uint32_t vendor_id;
- uint32_t vendor_rev;
+ u32_t oem_rev;
+ u32_t vendor_id;
+ u32_t vendor_rev;
} ACPI_TABLE_PACKED acpi_sdthdr_t;
typedef struct acpi_rsdt
{
uint16_t options;
uint16_t prdt_len;
- uint32_t transferred_size;
- uint32_t cmd_table_base;
- uint32_t reserved[5];
+ u32_t transferred_size;
+ u32_t cmd_table_base;
+ u32_t reserved[5];
} __HBA_PACKED__;
#define HBA_PRDTE_BYTE_CNT(cnt) ((cnt & 0x3FFFFF) | 0x1)
struct hba_prdte
{
- uint32_t data_base;
- uint32_t reserved[2];
- uint32_t byte_count;
+ u32_t data_base;
+ u32_t reserved[2];
+ u32_t byte_count;
} __HBA_PACKED__;
struct hba_cmdt
{
char serial_num[20];
char model[40];
- uint32_t flags;
+ u32_t flags;
uint64_t max_lba;
- uint32_t block_size;
+ u32_t block_size;
uint64_t wwn;
uint8_t cbd_size;
struct
uint8_t status;
uint8_t reserve;
} last_result;
- uint32_t alignment_offset;
- uint32_t block_per_sec;
- uint32_t capabilities;
+ u32_t alignment_offset;
+ u32_t block_per_sec;
+ u32_t capabilities;
struct hba_port* port;
struct ahci_hba* hba;
{
uint8_t opcode;
uint8_t misc1;
- uint32_t lba_be;
- uint32_t length;
+ u32_t lba_be;
+ u32_t length;
uint8_t misc2;
uint8_t ctrl;
} __attribute__((packed));
{
uint8_t opcode;
uint8_t misc1;
- uint32_t lba_be_hi;
- uint32_t lba_be_lo;
- uint32_t length;
+ u32_t lba_be_hi;
+ u32_t lba_be_lo;
+ u32_t length;
uint8_t misc2;
uint8_t ctrl;
} __attribute__((packed));
void
scsi_create_packet12(struct scsi_cdb12* cdb,
uint8_t opcode,
- uint32_t lba,
- uint32_t alloc_size);
+ u32_t lba,
+ u32_t alloc_size);
void
scsi_create_packet16(struct scsi_cdb16* cdb,
uint8_t opcode,
uint64_t lba,
- uint32_t alloc_size);
+ u32_t alloc_size);
void
scsi_submit(struct hba_device* dev, struct blkio_req* io_req);
void
-scsi_parse_capacity(struct hba_device* device, uint32_t* parameter);
+scsi_parse_capacity(struct hba_device* device, u32_t* parameter);
#endif /* __LUNAIX_ATAPI_H */
#ifndef __LUNAIX_CPU_H
#define __LUNAIX_CPU_H
-#include <stdint.h>
+#include <lunaix/types.h>
#define SEL_RPL(selector) ((selector)&0x3)
}
void
-cpu_rdmsr(uint32_t msr_idx, uint32_t* reg_high, uint32_t* reg_low);
+cpu_rdmsr(u32_t msr_idx, u32_t* reg_high, u32_t* reg_low);
void
-cpu_wrmsr(uint32_t msr_idx, uint32_t reg_high, uint32_t reg_low);
+cpu_wrmsr(u32_t msr_idx, u32_t reg_high, u32_t reg_low);
#endif
\ No newline at end of file
#ifndef __LUNAIX_IO_H
#define __LUNAIX_IO_H
-#include <stdint.h>
+#include <lunaix/types.h>
static inline uint8_t
io_inb(int port)
: "memory", "cc");
}
-static inline uint32_t
+static inline u32_t
io_inl(int port)
{
- uint32_t data;
+ u32_t data;
asm volatile("inl %w1,%0" : "=a"(data) : "d"(port));
return data;
}
}
static inline void
-io_outl(int port, uint32_t data)
+io_outl(int port, u32_t data)
{
asm volatile("outl %0,%w1" : : "a"(data), "d"(port));
}
static inline void
io_delay(int counter)
{
- asm volatile (
- " test %0, %0\n"
- " jz 1f\n"
- "2: dec %0\n"
- " jnz 2b\n"
- "1: dec %0"::"a"(counter));
+ asm volatile(" test %0, %0\n"
+ " jz 1f\n"
+ "2: dec %0\n"
+ " jnz 2b\n"
+ "1: dec %0" ::"a"(counter));
}
#endif /* __LUNAIX_IO_H */
ioapic_init();
void
-ioapic_write(uint8_t sel, uint32_t val);
+ioapic_write(uint8_t sel, u32_t val);
-uint32_t
+u32_t
ioapic_read(uint8_t sel);
void
-ioapic_redirect(uint8_t irq, uint8_t vector, uint8_t dest, uint32_t flags);
+ioapic_redirect(uint8_t irq, uint8_t vector, uint8_t dest, u32_t flags);
#endif /* __LUNAIX_IOAPIC_H */
struct pci_base_addr
{
- uint32_t start;
- uint32_t size;
- uint32_t type;
+ u32_t start;
+ u32_t size;
+ u32_t type;
};
struct pci_device
{
struct llist_header dev_chain;
- uint32_t device_info;
- uint32_t class_info;
- uint32_t cspace_base;
- uint32_t msi_loc;
+ u32_t device_info;
+ u32_t class_info;
+ u32_t cspace_base;
+ u32_t msi_loc;
uint16_t intr_info;
struct
{
// Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
static inline pci_reg_t
-pci_read_cspace(uint32_t base, int offset)
+pci_read_cspace(u32_t base, int offset)
{
io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
return io_inl(PCI_CONFIG_DATA);
}
static inline void
-pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
+pci_write_cspace(u32_t base, int offset, pci_reg_t data)
{
io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
io_outl(PCI_CONFIG_DATA, data);
*
* @return struct pci_device*
*/
-struct pci_device* pci_get_device_by_class(uint32_t class);
+struct pci_device* pci_get_device_by_class(u32_t class);
/**
* @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
* @return size_t
*/
size_t
-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
/**
* @brief 配置并启用设备MSI支持。
#ifndef __LUNAIX_HASH_H
#define __LUNAIX_HASH_H
-#include <stdint.h>
+#include <lunaix/types.h>
#define HASH_SIZE_BITS 32
-uint32_t
-strhash_32(const char* str, uint32_t truncate_to);
+u32_t
+strhash_32(const char* str, u32_t truncate_to);
/**
* @brief Simple generic hash function
* https://elixir.bootlin.com/linux/v5.18.12/source/include/linux/hash.h#L60
*
* @param val
- * @return uint32_t
+ * @return u32_t
*/
-inline uint32_t
-hash_32(const uint32_t val, uint32_t truncate_to)
+inline u32_t
+hash_32(const u32_t val, u32_t truncate_to)
{
return (val * 0x61C88647u) >> (HASH_SIZE_BITS - truncate_to);
}
} __attribute__((packed));
typedef u64_t partition_t;
-typedef uint32_t bdev_t;
+typedef u32_t bdev_t;
typedef void (*devfs_exporter)(struct block_dev* bdev, void* fsnode);
void
#include <lunaix/types.h>
-typedef uint32_t time_t;
+typedef u32_t time_t;
typedef struct
{
- uint32_t year; // use int32 as we need to store the 4-digit year
+ u32_t year; // use int32 as we need to store the 4-digit year
uint8_t month;
uint8_t day;
uint8_t weekday;
struct device
{
- uint32_t magic;
+ u32_t magic;
struct llist_header siblings;
struct llist_header children;
struct device* parent;
int (*write)(struct device* dev, void* buf, size_t offset, size_t len);
int (*read_page)(struct device* dev, void* buf, size_t offset);
int (*write_page)(struct device* dev, void* buf, size_t offset);
- int (*exec_cmd)(struct device* dev, uint32_t req, va_list args);
+ int (*exec_cmd)(struct device* dev, u32_t req, va_list args);
};
struct device*
device_add(struct device* parent,
void* underlay,
char* name_fmt,
- uint32_t type,
+ u32_t type,
va_list args);
struct device*
struct llist_header siblings;
struct llist_header nodes;
struct btrie_node* parent;
- uint32_t index;
+ u32_t index;
void* data;
};
void
-btrie_init(struct btrie* btrie, uint32_t trunc_bits);
+btrie_init(struct btrie* btrie, u32_t trunc_bits);
void*
-btrie_get(struct btrie* root, uint32_t index);
+btrie_get(struct btrie* root, u32_t index);
void
-btrie_set(struct btrie* root, uint32_t index, void* data);
+btrie_set(struct btrie* root, u32_t index, void* data);
void*
-btrie_remove(struct btrie* root, uint32_t index);
+btrie_remove(struct btrie* root, u32_t index);
void
btrie_release(struct btrie* tree);
struct hstr
{
- uint32_t hash;
- uint32_t len;
+ u32_t hash;
+ u32_t len;
const char* value;
};
#define HSTR_EQ(str1, str2) ((str1)->hash == (str2)->hash)
inline void
-hstr_rehash(struct hstr* hash_str, uint32_t truncate_to)
+hstr_rehash(struct hstr* hash_str, u32_t truncate_to)
{
hash_str->hash = strhash_32(hash_str->value, truncate_to);
}
{
struct llist_header lead_node;
struct llist_header zones;
- uint32_t objects;
+ u32_t objects;
evict_cb try_evict;
};
lru_use_one(dnode_lru, &dnode->lru); \
})
-typedef uint32_t inode_t;
+typedef u32_t inode_t;
struct v_dnode;
struct v_inode;
{
struct hlist_node fs_list;
struct hstr fs_name;
- uint32_t types;
+ u32_t types;
int fs_id;
int (*mount)(struct v_superblock* vsb, struct v_dnode* mount_point);
int (*unmount)(struct v_superblock* vsb);
struct device* dev;
struct v_dnode* root;
struct filesystem* fs;
- uint32_t iobuf_size;
+ u32_t iobuf_size;
struct hbucket* i_cache;
void* data;
struct
{
- uint32_t (*read_capacity)(struct v_superblock* vsb);
- uint32_t (*read_usage)(struct v_superblock* vsb);
+ u32_t (*read_capacity)(struct v_superblock* vsb);
+ u32_t (*read_usage)(struct v_superblock* vsb);
void (*init_inode)(struct v_superblock* vsb, struct v_inode* inode);
} ops;
};
struct v_inode* inode;
struct v_dnode* dnode;
struct llist_header* f_list;
- uint32_t f_pos;
+ u32_t f_pos;
atomic_ulong ref_count;
struct v_file_ops* ops; // for caching
};
{
inode_t id;
mutex_t lock;
- uint32_t itype;
+ u32_t itype;
time_t ctime;
time_t mtime;
time_t atime;
lba_t lb_addr;
- uint32_t open_count;
- uint32_t link_count;
- uint32_t lb_usage;
- uint32_t fsize;
+ u32_t open_count;
+ u32_t link_count;
+ u32_t lb_usage;
+ u32_t fsize;
void* data; // 允许底层FS绑定他的一些专有数据
struct llist_header aka_dnodes;
struct llist_header xattrs;
struct v_mount* parent;
struct v_dnode* mnt_point;
struct v_superblock* super_block;
- uint32_t busy_counter;
+ u32_t busy_counter;
int flags;
};
struct btrie tree;
struct llist_header pages;
struct llist_header dirty;
- uint32_t n_dirty;
- uint32_t n_pages;
+ u32_t n_dirty;
+ u32_t n_pages;
};
struct pcache_pg
struct lru_node lru;
struct pcache* holder;
void* pg;
- uint32_t flags;
- uint32_t fpos;
- uint32_t len;
+ u32_t flags;
+ u32_t fpos;
+ u32_t len;
};
void
vfs_d_free(struct v_dnode* dnode);
struct v_inode*
-vfs_i_find(struct v_superblock* sb, uint32_t i_id);
+vfs_i_find(struct v_superblock* sb, u32_t i_id);
void
vfs_i_addhash(struct v_inode* inode);
pcache_release_page(struct pcache* pcache, struct pcache_pg* page);
struct pcache_pg*
-pcache_new_page(struct pcache* pcache, uint32_t index);
+pcache_new_page(struct pcache* pcache, u32_t index);
void
pcache_set_dirty(struct pcache* pcache, struct pcache_pg* pg);
int
pcache_get_page(struct pcache* pcache,
- uint32_t index,
- uint32_t* offset,
+ u32_t index,
+ u32_t* offset,
struct pcache_pg** page);
int
-pcache_write(struct v_inode* inode, void* data, uint32_t len, uint32_t fpos);
+pcache_write(struct v_inode* inode, void* data, u32_t len, u32_t fpos);
int
-pcache_read(struct v_inode* inode, void* data, uint32_t len, uint32_t fpos);
+pcache_read(struct v_inode* inode, void* data, u32_t len, u32_t fpos);
void
pcache_release(struct pcache* pcache);
struct hstr name;
inode_t ino_id;
void* data;
- uint32_t itype;
+ u32_t itype;
char name_val[VFS_NAME_MAXLEN];
struct llist_header children;
struct llist_header siblings;
struct input_evt_pkt
{
- uint32_t pkt_type; // packet type
- uint32_t scan_code; // hardware raw code
- uint32_t sys_code; // driver translated code
- time_t timestamp; // event timestamp
+ u32_t pkt_type; // packet type
+ u32_t scan_code; // hardware raw code
+ u32_t sys_code; // driver translated code
+ time_t timestamp; // event timestamp
};
struct input_device
#define PACK(size, flags) (((size) & ~0x3) | (flags))
-#define SW(p, w) (*((uint32_t*)(p)) = w)
-#define LW(p) (*((uint32_t*)(p)))
+#define SW(p, w) (*((u32_t*)(p)) = w)
+#define LW(p) (*((u32_t*)(p)))
-#define HPTR(bp) ((uint32_t*)(bp)-1)
+#define HPTR(bp) ((u32_t*)(bp)-1)
#define BPTR(bp) ((uint8_t*)(bp) + WSIZE)
-#define FPTR(hp, size) ((uint32_t*)(hp + size - WSIZE))
+#define FPTR(hp, size) ((u32_t*)(hp + size - WSIZE))
#define NEXT_CHK(hp) ((uint8_t*)(hp) + CHUNK_S(LW(hp)))
#define BOUNDARY 4
#ifndef __LUNAIX_MMIO_H
#define __LUNAIX_MMIO_H
-#include <stdint.h>
+#include <lunaix/types.h>
void*
-ioremap(uintptr_t paddr, uint32_t size);
+ioremap(uintptr_t paddr, u32_t size);
void*
-iounmap(uintptr_t vaddr, uint32_t size);
+iounmap(uintptr_t vaddr, u32_t size);
#endif /* __LUNAIX_MMIO_H */
#ifndef __LUNAIX_PAGE_H
#define __LUNAIX_PAGE_H
#include <lunaix/common.h>
-#include <stdint.h>
+#include <lunaix/types.h>
#define PG_MAX_ENTRIES 1024U
#define PG_LAST_TABLE PG_MAX_ENTRIES - 1
#define PG_ALIGN(addr) ((uintptr_t)(addr)&0xFFFFF000UL)
-#define L1_INDEX(vaddr) (uint32_t)(((uintptr_t)(vaddr)&0xFFC00000UL) >> 22)
-#define L2_INDEX(vaddr) (uint32_t)(((uintptr_t)(vaddr)&0x003FF000UL) >> 12)
-#define PG_OFFSET(vaddr) (uint32_t)((uintptr_t)(vaddr)&0x00000FFFUL)
+#define L1_INDEX(vaddr) (u32_t)(((uintptr_t)(vaddr)&0xFFC00000UL) >> 22)
+#define L2_INDEX(vaddr) (u32_t)(((uintptr_t)(vaddr)&0x003FF000UL) >> 12)
+#define PG_OFFSET(vaddr) (u32_t)((uintptr_t)(vaddr)&0x00000FFFUL)
#define GET_PT_ADDR(pde) PG_ALIGN(pde)
#define GET_PG_ADDR(pte) PG_ALIGN(pte)
typedef unsigned long ptd_t;
typedef unsigned long pt_t;
typedef unsigned int pt_attr;
-typedef uint32_t x86_pte_t;
+typedef u32_t x86_pte_t;
/**
* @brief 虚拟映射属性
// 虚拟页地址
uintptr_t va;
// 物理页码（如果不存在映射，则为0）
- uint32_t pn;
+ u32_t pn;
// 物理页地址（如果不存在映射，则为0）
uintptr_t pa;
// 映射的flags
*/
#define PP_FGLOCKED 0x2
-typedef uint32_t pp_attr_t;
+typedef u32_t pp_attr_t;
struct pp_struct
{
pid_t owner;
- uint32_t ref_counts;
+ u32_t ref_counts;
pp_attr_t attr;
};
*/
void
pmm_mark_chunk_occupied(pid_t owner,
- uintptr_t start_ppn,
+ u32_t start_ppn,
size_t page_count,
pp_attr_t attr);
#define TIMER_MODE_PERIODIC 0x1
-typedef uint32_t ticks_t;
+typedef u32_t ticks_t;
struct lx_timer_context
{
* @brief Desired system running frequency
*
*/
- uint32_t running_frequency;
+ u32_t running_frequency;
/**
* @brief Ticks per hertz
*
* @param frequency The frequency that timer should run in Hz.
*/
void
-timer_init(uint32_t frequency);
+timer_init(u32_t frequency);
struct lx_timer*
-timer_run_second(uint32_t second,
+timer_run_second(u32_t second,
void (*callback)(void*),
void* payload,
uint8_t flags);
struct lx_timer*
-timer_run_ms(uint32_t millisecond,
+timer_run_ms(u32_t millisecond,
void (*callback)(void*),
void* payload,
uint8_t flags);
#include <arch/x86/gdt.h>
#include <arch/x86/tss.h>
-#include <stdint.h>
+#include <lunaix/types.h>
#define GDT_ENTRY 6
uint64_t _gdt[GDT_ENTRY];
uint16_t _gdt_limit = sizeof(_gdt) - 1;
-void _set_gdt_entry(uint32_t index, uint32_t base, uint32_t limit, uint32_t flags) {
- _gdt[index] = SEG_BASE_H(base) | flags | SEG_LIM_H(limit) | SEG_BASE_M(base);
+void
+_set_gdt_entry(u32_t index, u32_t base, u32_t limit, u32_t flags)
+{
+ _gdt[index] =
+ SEG_BASE_H(base) | flags | SEG_LIM_H(limit) | SEG_BASE_M(base);
_gdt[index] <<= 32;
_gdt[index] |= SEG_BASE_L(base) | SEG_LIM_L(limit);
}
extern struct x86_tss _tss;
void
-_init_gdt() {
+_init_gdt()
+{
_set_gdt_entry(0, 0, 0, 0);
_set_gdt_entry(1, 0, 0xfffff, SEG_R0_CODE);
_set_gdt_entry(2, 0, 0xfffff, SEG_R0_DATA);
extern void
intr_routine_page_fault(const isr_param* param);
-extern uint32_t debug_resv;
+extern u32_t debug_resv;
void
__print_panic_msg(const char* msg, const isr_param* param)
void
intr_routine_apic_error(const isr_param* param)
{
- uint32_t error_reg = apic_read_reg(APIC_ESR);
+ u32_t error_reg = apic_read_reg(APIC_ESR);
char buf[32];
ksprintf(buf, "APIC error, ESR=0x%x", error_reg);
console_flush();
#include <arch/x86/idt.h>
-#include <stdint.h>
#include <arch/x86/intrhnds.h>
+#include <lunaix/types.h>
#define IDT_ENTRY 256
uint64_t _idt[IDT_ENTRY];
uint16_t _idt_limit = sizeof(_idt) - 1;
static inline void
-_set_idt_entry(uint32_t vector,
+_set_idt_entry(u32_t vector,
uint16_t seg_selector,
void (*isr)(),
uint8_t dpl,
_idt[vector] |= (seg_selector << 16) | (offset & 0x0000ffff);
}
-void _init_idt() {
+void
+_init_idt()
+{
_set_idt_entry(0, 8, _asm_isr0, 0, IDT_INTERRUPT);
_set_idt_entry(1, 8, _asm_isr1, 0, IDT_INTERRUPT);
_set_idt_entry(2, 8, _asm_isr2, 0, IDT_INTERRUPT);
.ss0 = KDATA_SEG };
void
-tss_update_esp(uint32_t esp0)
+tss_update_esp(u32_t esp0)
{
_tss.esp0 = esp0;
}
\ No newline at end of file
device_add(struct device* parent,
void* underlay,
char* name_fmt,
- uint32_t type,
+ u32_t type,
va_list args)
{
struct device* dev = vzalloc(sizeof(struct device));
#define BTRIE_INSERT 1
struct btrie_node*
-__btrie_traversal(struct btrie* root, uint32_t index, int options)
+__btrie_traversal(struct btrie* root, u32_t index, int options)
{
index = index >> root->truncated;
- uint32_t lz = index ? ROUNDDOWN(31 - __builtin_clz(index), BTRIE_BITS) : 0;
- uint32_t bitmask = ((1 << BTRIE_BITS) - 1) << lz;
- uint32_t i = 0;
+ u32_t lz = index ? ROUNDDOWN(31 - __builtin_clz(index), BTRIE_BITS) : 0;
+ u32_t bitmask = ((1 << BTRIE_BITS) - 1) << lz;
+ u32_t i = 0;
struct btrie_node* tree = root->btrie_root;
// Time complexity: O(log_2(log_2(N))) where N is the index to lookup
}
void
-btrie_init(struct btrie* btrie, uint32_t trunc_bits)
+btrie_init(struct btrie* btrie, u32_t trunc_bits)
{
btrie->btrie_root = vzalloc(sizeof(struct btrie_node));
llist_init_head(&btrie->btrie_root->nodes);
}
void*
-btrie_get(struct btrie* root, uint32_t index)
+btrie_get(struct btrie* root, u32_t index)
{
struct btrie_node* node = __btrie_traversal(root, index, 0);
if (!node) {
}
void
-btrie_set(struct btrie* root, uint32_t index, void* data)
+btrie_set(struct btrie* root, u32_t index, void* data)
{
struct btrie_node* node = __btrie_traversal(root, index, BTRIE_INSERT);
node->data = data;
}
void*
-btrie_remove(struct btrie* root, uint32_t index)
+btrie_remove(struct btrie* root, u32_t index)
{
struct btrie_node* node = __btrie_traversal(root, index, 0);
if (!node) {
extern void
iso9660_init_inode(struct v_superblock* vsb, struct v_inode* inode);
-uint32_t
+u32_t
iso9660_rd_capacity(struct v_superblock* vsb)
{
struct iso_superblock* isovsb = (struct iso_superblock*)vsb->data;
}
struct pcache_pg*
-pcache_new_page(struct pcache* pcache, uint32_t index)
+pcache_new_page(struct pcache* pcache, u32_t index)
{
struct pcache_pg* ppg = vzalloc(sizeof(struct pcache_pg));
void* pg = valloc(PG_SIZE);
int
pcache_get_page(struct pcache* pcache,
- uint32_t index,
- uint32_t* offset,
+ u32_t index,
+ u32_t* offset,
struct pcache_pg** page)
{
struct pcache_pg* pg = btrie_get(&pcache->tree, index);
}
int
-pcache_write(struct v_inode* inode, void* data, uint32_t len, uint32_t fpos)
+pcache_write(struct v_inode* inode, void* data, u32_t len, u32_t fpos)
{
- uint32_t pg_off, buf_off = 0;
+ u32_t pg_off, buf_off = 0;
struct pcache* pcache = inode->pg_cache;
struct pcache_pg* pg;
return ENOMEM;
}
- uint32_t wr_bytes = MIN(PG_SIZE - pg_off, len - buf_off);
+ u32_t wr_bytes = MIN(PG_SIZE - pg_off, len - buf_off);
memcpy(pg->pg + pg_off, (data + buf_off), wr_bytes);
pcache_set_dirty(pcache, pg);
}
int
-pcache_read(struct v_inode* inode, void* data, uint32_t len, uint32_t fpos)
+pcache_read(struct v_inode* inode, void* data, u32_t len, u32_t fpos)
{
- uint32_t pg_off, buf_off = 0, new_pg = 0;
+ u32_t pg_off, buf_off = 0, new_pg = 0;
int errno = 0;
struct pcache* pcache = inode->pg_cache;
struct pcache_pg* pg;
}
pg->len = errno;
}
- uint32_t rd_bytes = MIN(pg->len - pg_off, len - buf_off);
+ u32_t rd_bytes = MIN(pg->len - pg_off, len - buf_off);
if (!rd_bytes)
break;
static struct cake_pile* twi_pile;
-static volatile uint32_t inode_id = 0;
+static volatile u32_t inode_id = 0;
extern const struct v_file_ops twifs_file_ops;
extern const struct v_inode_ops twifs_inode_ops;
__twifs_new_node(struct twifs_node* parent,
const char* name,
int name_len,
- uint32_t itype)
+ u32_t itype)
{
struct twifs_node* node = cake_grab(twi_pile);
memset(node, 0, sizeof(*node));
}
inline struct hbucket*
-__dcache_hash(struct v_dnode* parent, uint32_t* hash)
+__dcache_hash(struct v_dnode* parent, u32_t* hash)
{
- uint32_t _hash = *hash;
+ u32_t _hash = *hash;
// 确保低位更加随机
_hash = _hash ^ (_hash >> VFS_HASHBITS);
// 与parent的指针值做加法，来减小碰撞的可能性。
- _hash += (uint32_t)parent;
+ _hash += (u32_t)parent;
*hash = _hash;
return &dnode_cache[_hash & VFS_HASH_MASK];
}
return parent->parent;
}
- uint32_t hash = str->hash;
+ u32_t hash = str->hash;
struct hbucket* slot = __dcache_hash(parent, &hash);
struct v_dnode *pos, *n;
}
struct v_inode*
-vfs_i_find(struct v_superblock* sb, uint32_t i_id)
+vfs_i_find(struct v_superblock* sb, u32_t i_id)
{
struct hbucket* slot = &sb->i_cache[i_id & VFS_HASH_MASK];
struct v_inode *pos, *n;
// mutex_lock(&kheap.lock);
// uint8_t* chunk_ptr = (uint8_t*)ptr - WSIZE;
-// uint32_t hdr = LW(chunk_ptr);
+// u32_t hdr = LW(chunk_ptr);
// size_t sz = CHUNK_S(hdr);
// uint8_t* next_hdr = chunk_ptr + sz;
// // and space for header
// size = ROUNDUP(size + WSIZE, BOUNDARY);
// while (ptr < (uint8_t*)heap->brk) {
-// uint32_t header = *((uint32_t*)ptr);
+// u32_t header = *((u32_t*)ptr);
// size_t chunk_size = CHUNK_S(header);
// if (!chunk_size && CHUNK_A(header)) {
// break;
// void
// place_chunk(uint8_t* ptr, size_t size)
// {
-// uint32_t header = *((uint32_t*)ptr);
+// u32_t header = *((u32_t*)ptr);
// size_t chunk_size = CHUNK_S(header);
-// *((uint32_t*)ptr) = PACK(size, CHUNK_PF(header) | M_ALLOCATED);
+// *((u32_t*)ptr) = PACK(size, CHUNK_PF(header) | M_ALLOCATED);
// uint8_t* n_hdrptr = (uint8_t*)(ptr + size);
-// uint32_t diff = chunk_size - size;
+// u32_t diff = chunk_size - size;
// if (!diff) {
// // if the current free block is fully occupied
-// uint32_t n_hdr = LW(n_hdrptr);
+// u32_t n_hdr = LW(n_hdrptr);
// // notify the next block about our avaliability
// SW(n_hdrptr, n_hdr & ~0x2);
// } else {
// // if there is remaining free space left
-// uint32_t remainder_hdr = PACK(diff, M_NOT_ALLOCATED |
+// u32_t remainder_hdr = PACK(diff, M_NOT_ALLOCATED |
// M_PREV_ALLOCATED); SW(n_hdrptr, remainder_hdr); SW(FPTR(n_hdrptr,
// diff), remainder_hdr);
// void*
// coalesce(uint8_t* chunk_ptr)
// {
-// uint32_t hdr = LW(chunk_ptr);
-// uint32_t pf = CHUNK_PF(hdr);
-// uint32_t sz = CHUNK_S(hdr);
+// u32_t hdr = LW(chunk_ptr);
+// u32_t pf = CHUNK_PF(hdr);
+// u32_t sz = CHUNK_S(hdr);
-// uint32_t n_hdr = LW(chunk_ptr + sz);
+// u32_t n_hdr = LW(chunk_ptr + sz);
// if (CHUNK_A(n_hdr) && pf) {
// // case 1: prev is free
-// uint32_t prev_ftr = LW(chunk_ptr - WSIZE);
+// u32_t prev_ftr = LW(chunk_ptr - WSIZE);
// size_t prev_chunk_sz = CHUNK_S(prev_ftr);
-// uint32_t new_hdr = PACK(prev_chunk_sz + sz, CHUNK_PF(prev_ftr));
+// u32_t new_hdr = PACK(prev_chunk_sz + sz, CHUNK_PF(prev_ftr));
// SW(chunk_ptr - prev_chunk_sz, new_hdr);
// SW(FPTR(chunk_ptr, sz), new_hdr);
// chunk_ptr -= prev_chunk_sz;
// } else if (!CHUNK_A(n_hdr) && !pf) {
// // case 2: next is free
// size_t next_chunk_sz = CHUNK_S(n_hdr);
-// uint32_t new_hdr = PACK(next_chunk_sz + sz, pf);
+// u32_t new_hdr = PACK(next_chunk_sz + sz, pf);
// SW(chunk_ptr, new_hdr);
// SW(FPTR(chunk_ptr, sz + next_chunk_sz), new_hdr);
// } else if (!CHUNK_A(n_hdr) && pf) {
// // case 3: both free
-// uint32_t prev_ftr = LW(chunk_ptr - WSIZE);
+// u32_t prev_ftr = LW(chunk_ptr - WSIZE);
// size_t next_chunk_sz = CHUNK_S(n_hdr);
// size_t prev_chunk_sz = CHUNK_S(prev_ftr);
-// uint32_t new_hdr =
+// u32_t new_hdr =
// PACK(next_chunk_sz + prev_chunk_sz + sz, CHUNK_PF(prev_ftr));
// SW(chunk_ptr - prev_chunk_sz, new_hdr);
// SW(FPTR(chunk_ptr, sz + next_chunk_sz), new_hdr);
// // minus the overhead for epilogue, keep the invariant.
// heap->brk -= WSIZE;
-// uint32_t old_marker = *((uint32_t*)start);
-// uint32_t free_hdr = PACK(sz, CHUNK_PF(old_marker));
+// u32_t old_marker = *((u32_t*)start);
+// u32_t free_hdr = PACK(sz, CHUNK_PF(old_marker));
// SW(start, free_hdr);
// SW(FPTR(start, sz), free_hdr);
// SW(NEXT_CHK(start), PACK(0, M_ALLOCATED | M_PREV_FREE));
#include <lunaix/spike.h>
void*
-ioremap(uintptr_t paddr, uint32_t size)
+ioremap(uintptr_t paddr, u32_t size)
{
void* ptr = vmm_vmap(paddr, size, PG_PREM_RW | PG_DISABLE_CACHE);
if (ptr) {
}
void*
-iounmap(uintptr_t vaddr, uint32_t size)
+iounmap(uintptr_t vaddr, u32_t size)
{
for (size_t i = 0; i < size; i += PG_SIZE) {
uintptr_t paddr = vmm_del_mapping(PD_REFERENCED, vaddr + i);
void
pmm_mark_chunk_occupied(pid_t owner,
- uint32_t start_ppn,
+ u32_t start_ppn,
size_t page_count,
pp_attr_t attr)
{
{
(void*)owner; // TODO: do smth with owner
- uint32_t ppn = (uintptr_t)page >> 12;
+ u32_t ppn = (uintptr_t)page >> 12;
if (ppn >= PM_BMP_MAX_SIZE) {
return 0;
struct pp_struct*
pmm_query(void* pa)
{
- uint32_t ppn = (uintptr_t)pa >> 12;
+ u32_t ppn = (uintptr_t)pa >> 12;
if (ppn >= PM_BMP_MAX_SIZE) {
return NULL;
{
assert(((uintptr_t)va & 0xFFFU) == 0);
- uint32_t l1_index = L1_INDEX(va);
- uint32_t l2_index = L2_INDEX(va);
+ u32_t l1_index = L1_INDEX(va);
+ u32_t l2_index = L2_INDEX(va);
// prevent unmap of recursive mapping region
if (l1_index == 1023) {
int
vmm_lookup(uintptr_t va, v_mapping* mapping)
{
- uint32_t l1_index = L1_INDEX(va);
- uint32_t l2_index = L2_INDEX(va);
+ u32_t l1_index = L1_INDEX(va);
+ u32_t l2_index = L2_INDEX(va);
x86_page_table* l1pt = (x86_page_table*)L1_BASE_VADDR;
x86_pte_t l1pte = l1pt->entry[l1_index];
void*
vmm_v2p(void* va)
{
- uint32_t l1_index = L1_INDEX(va);
- uint32_t l2_index = L2_INDEX(va);
+ u32_t l1_index = L1_INDEX(va);
+ u32_t l2_index = L2_INDEX(va);
x86_page_table* l1pt = (x86_page_table*)L1_BASE_VADDR;
x86_pte_t l1pte = l1pt->entry[l1_index];
// Don't optimize them! Took me an half hour to figure that out...
-static volatile uint32_t rtc_counter = 0;
+static volatile u32_t rtc_counter = 0;
static volatile uint8_t apic_timer_done = 0;
-static volatile uint32_t sched_ticks = 0;
-static volatile uint32_t sched_ticks_counter = 0;
+static volatile u32_t sched_ticks = 0;
+static volatile u32_t sched_ticks_counter = 0;
static struct cake_pile* timer_pile;
}
void
-timer_init(uint32_t frequency)
+timer_init(u32_t frequency)
{
timer_init_context();
// mapping config.
// grab ourselves these irq numbers
- uint32_t iv_rtc = isrm_bindirq(PC_AT_IRQ_RTC, temp_intr_routine_rtc_tick);
- uint32_t iv_timer = isrm_ivexalloc(temp_intr_routine_apic_timer);
+ u32_t iv_rtc = isrm_bindirq(PC_AT_IRQ_RTC, temp_intr_routine_rtc_tick);
+ u32_t iv_timer = isrm_ivexalloc(temp_intr_routine_apic_timer);
// Setup a one-shot timer, we will use this to measure the bus speed. So we
// can then calibrate apic timer to work at *nearly* accurate hz
}
struct lx_timer*
-timer_run_second(uint32_t second,
+timer_run_second(u32_t second,
void (*callback)(void*),
void* payload,
uint8_t flags)
}
struct lx_timer*
-timer_run_ms(uint32_t millisecond,
+timer_run_ms(u32_t millisecond,
void (*callback)(void*),
void* payload,
uint8_t flags)
int
__lxconsole_listener(struct input_device* dev)
{
- uint32_t key = dev->current_pkt.sys_code;
- uint32_t type = dev->current_pkt.pkt_type;
+ u32_t key = dev->current_pkt.sys_code;
+ u32_t type = dev->current_pkt.pkt_type;
kbd_kstate_t state = key >> 16;
ttychr = key & 0xff;
key = key & 0xffff;
}
int
-__tty_exec_cmd(struct device* dev, uint32_t req, va_list args)
+__tty_exec_cmd(struct device* dev, u32_t req, va_list args)
{
switch (req) {
case TIOCGPGRP:
if (x >= TTY_WIDTH || y >= TTY_HEIGHT) {
x = y = 0;
}
- uint32_t pos = y * TTY_WIDTH + x;
+ u32_t pos = y * TTY_WIDTH + x;
io_outb(0x3D4, 14);
io_outb(0x3D5, pos / 256);
io_outb(0x3D4, 15);
* @param str
* @return unsigned int
*/
-uint32_t
-strhash_32(const char* str, uint32_t truncate_to)
+u32_t
+strhash_32(const char* str, u32_t truncate_to)
{
if (!str)
return 0;
- uint32_t hash = 5381;
+ u32_t hash = 5381;
int c;
while ((c = *str++))
#include <klibc/stdio.h>
#include <klibc/stdlib.h>
#include <klibc/string.h>
-#include <stdint.h>
+#include <lunaix/types.h>
#define NUMBUFSIZ 24
// Of course, with some modifications for porting to LunaixOS :)
char numbuf[NUMBUFSIZ];
- uint32_t ptr = 0;
+ u32_t ptr = 0;
for (; *fmt; ++fmt) {
if (max_len && ptr >= max_len - 1) {
break;
uint64_t _idt[IDT_ENTRY];
uint16_t _idt_limit = sizeof(_idt) - 1;
static inline void
-_set_idt_entry(uint32_t vector,
+_set_idt_entry(u32_t vector,
uint16_t seg_selector,
void (*isr)(),
uint8_t dpl,
git://scm.lunaixsky.com / lunaix-os.git / commitdiff