feat: BAR sizing and MSI configuration

refactor: Add some useful comments

diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c
index 90011c6eb200a4ebcdca165afe2d74cda52e9d09..dd4e95b88b0eb156c03f5270471564eb0b3cb4fb 100644 (file)
--- a/lunaix-os/hal/pci.c
+++ b/lunaix-os/hal/pci.c
@@ -1,3 +1,4 @@
+#include <hal/apic.h>
 #include <hal/pci.h>
 #include <lunaix/mm/kalloc.h>
 #include <lunaix/syslog.h>
@@ -31,7 +32,7 @@ pci_probe_device(int bus, int dev, int funct)
         }
     }
 
-    if (hdr_type != 0) {
+    if (hdr_type != PCI_TDEV) {
         // XXX: 目前忽略所有桥接设备，比如PCI-PCI桥接器，或者是CardBus桥接器
         return;
     }
@@ -87,6 +88,8 @@ pci_probe_msi_info(struct pci_device* device)
     }
 }
 
+#define PCI_PRINT_BAR_LISTING
+
 void
 pci_print_device()
 {
@@ -104,13 +107,71 @@ pci_print_device()
         kprintf(KINFO "\t IRQ: %d, INT#x: %d\n",
                 PCI_INTR_IRQ(pos->intr_info),
                 PCI_INTR_PIN(pos->intr_info));
-
+#ifdef PCI_PRINT_BAR_LISTING
+        pci_reg_t bar;
+        for (size_t i = 1; i <= 6; i++) {
+            size_t size = pci_bar_sizing(pos, &bar, i);
+            if (!bar)
+                continue;
+            if (PCI_BAR_MMIO(bar)) {
+                kprintf(KINFO "\t BAR#%d (MMIO) %p [%d]\n",
+                        i,
+                        PCI_BAR_ADDR_MM(bar),
+                        size);
+            } else {
+                kprintf(KINFO "\t BAR#%d (I/O) %p [%d]\n",
+                        i,
+                        PCI_BAR_ADDR_IO(bar),
+                        size);
+            }
+        }
+#endif
         if (pos->msi_loc) {
             kprintf(KINFO "\t MSI supported (@%xh)\n", pos->msi_loc);
         }
     }
 }
 
+size_t
+pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
+{
+    pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num));
+    if (!bar) {
+        *bar_out = 0;
+        return 0;
+    }
+
+    pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), 0xffffffff);
+    pci_reg_t sized =
+      pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)) & ~0x1;
+    if (PCI_BAR_MMIO(bar)) {
+        sized = PCI_BAR_ADDR_MM(sized);
+    }
+    *bar_out = bar;
+    return ~sized + 1;
+}
+
+void
+pci_setup_msi(struct pci_device* device, int vector)
+{
+    // Dest: APIC#0, Physical Destination, No redirection
+    uint32_t msi_addr = (__APIC_BASE_PADDR | 0x8);
+
+    // Edge trigger, Fixed delivery
+    uint32_t msi_data = vector;
+
+    pci_write_cspace(
+      device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
+    pci_write_cspace(
+      device->cspace_base, PCI_MSI_DATA(device->msi_loc), msi_data & 0xffff);
+
+    pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
+
+    // manipulate the MSI_CTRL to allow device using MSI to request service.
+    reg1 = ((((reg1 >> 16) & ~0x70) | 0x1) << 16) | (reg1 & 0xffff);
+    pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
+}
+
 struct pci_device*
 pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId)
 {

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index bd203590100e8c48e8b473fbb47d7ecc295efc31..639a12c4de271febd0897b3aa3c7b18896268f58 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -15,7 +15,7 @@
 
 #define PCI_REG_VENDOR_DEV 0
 #define PCI_REG_STATUS_CMD 0x4
-#define PCI_REG_BAR(offset) (0x10 + (offset)*4)
+#define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 
 #define PCI_DEV_VENDOR(x) ((x)&0xffff)
 #define PCI_DEV_DEVID(x) ((x) >> 16)
@@ -23,9 +23,18 @@
 #define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
 #define PCI_DEV_CLASS(x) ((x) >> 8)
 #define PCI_DEV_REV(x) (((x)&0xff))
-#define PCI_BUS_NUM(x) ((x >> 16) & 0xff)
-#define PCI_SLOT_NUM(x) ((x >> 11) & 0x1f)
-#define PCI_FUNCT_NUM(x) ((x >> 8) & 0x7)
+#define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
+#define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
+#define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
+
+#define PCI_BAR_MMIO(x) (!((x)&0x1))
+#define PCI_BAR_CACHEABLE(x) ((x)&0x8)
+#define PCI_BAR_TYPE(x) ((x)&0x6)
+#define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
+#define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
+
+#define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
+#define PCI_MSI_DATA(msi_base) ((msi_base) + 8)
 
 #define PCI_ADDRESS(bus, dev, funct)                                           \
     (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
@@ -63,18 +72,57 @@ pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
     io_outl(PCI_CONFIG_DATA, data);
 }
 
-void
-pci_probe();
-
+/**
+ * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该
+ * 初始化不包括针对每个设备的初始化，因为那是设备驱动的事情。
+ *
+ */
 void
 pci_init();
 
 void
 pci_print_device();
 
+/**
+ * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
+ * 类型代码请参阅： PCI LB Spec. Appendix D.
+ *
+ * @return struct pci_device*
+ */
 struct pci_device* pci_get_device_by_class(uint32_t class);
 
+/**
+ * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
+ *
+ * @param vendorId
+ * @param deviceId
+ * @return struct pci_device*
+ */
 struct pci_device*
 pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
 
+/**
+ * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
+ * 设备所使用的MMIO或I/O地址空间的，大小。
+ * 参阅：PCI LB Spec. (Rev 3) Section 6.2.5.1, Implementation Note.
+ *
+ * @param dev The PCI device
+ * @param bar_out Value in BAR
+ * @param bar_num The index of BAR (starting from 1)
+ * @return size_t
+ */
+size_t
+pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
+
+/**
+ * @brief 配置并启用设备MSI支持。
+ * 参阅：PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
+ * 以及：Intel Manual, Vol 3, Section 10.11
+ *
+ * @param device PCI device
+ * @param vector interrupt vector.
+ */
+void
+pci_setup_msi(struct pci_device* device, int vector);
+
 #endif /* __LUNAIX_PCI_H */